MH

Ming-Chou Ho

ET Ememory Technology: 11 patents #24 of 169Top 15%
TSMC: 10 patents #2,782 of 12,232Top 25%
Overall (All Time): #210,625 of 4,157,543Top 6%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8089798 Method for operating one-time programmable read-only memory Tsung-Mu Lai, Shao-Chang Huang, Wen-Hao Ching, Chun-Hung Lu, Shih-Chen Wang 2012-01-03
7768059 Nonvolatile single-poly memory device Hsin-Ming Chen, Shih-Chen Wang, Shih-Jye Shen 2010-08-03
7447082 Method for operating single-poly non-volatile memory device Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Shih-Jye Shen, Ching-Hsiang Hsu 2008-11-04
7433243 Operation method of non-volatile memory Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Shih-Jye Shen, Ching-Hsiang Hsu 2008-10-07
6920067 Integrated circuit embedded with single-poly non-volatile memory Ching-Hsiang Hsu, Chih-Hsun Chu, Shih-Jye Shen 2005-07-19
6914825 Semiconductor memory device having improved data retention Ching-Hsiang Hsu, Shih-Jye Shen 2005-07-05
6842374 Method for operating N-channel electrically erasable programmable logic device Kung-Hong Lee, Ching-Hsiang Hsu, Ya-Chin King, Shih-Jye Shen 2005-01-11
6822286 Cmos-compatible read only memory and method for fabricating the same Ching-Hsiang Hsu, Wei-Zhe Wong, Shih-Jye Shen, Hsin-Ming Chen, Shih-Chan Huang 2004-11-23
6812083 Fabrication method for non-volatile memory Shih-Jye Shen, Wei-Zhe Wong, Hsin-Ming Chen 2004-11-02
6740556 Method for forming EPROM with low leakage Ching-Hsiang Hsu, Chih-Hsun Chu, Shih-Jye Shen 2004-05-25
6617637 Electrically erasable programmable logic device Ching-Hsiang Hsu, Yen-Tai Lin, Chih-Hsun Chu, Shih-Jye Shen, Ching-Sung Yang 2003-09-09
6417046 Modified nitride spacer for solving charge retention issue in floating gate memory cell Wen-Ting Chu, Chang-Song Lin, Chuan-Li Chang, Hsin-Ming Chen, Di-Son Kuo 2002-07-09
6303454 Process for a snap-back flash EEPROM cell Juang-Ker Yeh, Jian-Hsing Lee, Kuo-Reay Peng 2001-10-16
6117732 Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell Wen-Ting Chu, Chuan-Li Chang, Chang-Song Lin, Di-Son Kuo 2000-09-12
6055183 Erase method of flash EEPROM by using snapback characteristic Jian-Hsing Lee, Kuo-Reay Peng, Juang-Ke Yeh 2000-04-25
6049484 Erase method to improve flash EEPROM endurance by combining high voltage source erase and negative gate erase Jian-Hsing Lee, Kuo-Reay Peng, Juang-Ke Yeh 2000-04-11
5949717 Method to improve flash EEPROM cell write/erase threshold voltage closure Juang-Ker Yeh, Jian-Hsing Lee, Kuo-Reay Peng 1999-09-07
5903499 Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase Kuo-Reay Peng, Jian-Hsing Lee, Juang-Ke Yeh 1999-05-11
5862078 Mixed mode erase method to improve flash eeprom write/erase threshold closure Juang-Ker Yeh, Jian-Hsing Lee, Kuo-Reay Peng 1999-01-19
5838618 Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure Jian-Hsing Lee, Juang-Ker Yeh, Kuo-Reay Peng 1998-11-17
5726933 Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROM Jian-Hsing Lee, Kuo-Reay Peng, Juang-Ke Yeh 1998-03-10