Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6753569 | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation | Yai-Fen Lin, Chang-Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung | 2004-06-22 |
| 6509603 | P-channel EEPROM and flash EEPROM devices | Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo | 2003-01-21 |
| 6483159 | Undoped polysilicon as the floating-gate of a split-gate flash cell | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Di-Son Kuo | 2002-11-19 |
| 6358796 | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation | Yai-Fen Lin, Chang-Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung | 2002-03-19 |
| 6246089 | P-channel EEPROM devices | Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo | 2001-06-12 |
| 6121088 | Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Di-Son Kuo | 2000-09-19 |
| 6060360 | Method of manufacture of P-channel EEprom and flash EEprom devices | Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo | 2000-05-09 |
| 6055183 | Erase method of flash EEPROM by using snapback characteristic | Ming-Chou Ho, Jian-Hsing Lee, Kuo-Reay Peng | 2000-04-25 |
| 6049484 | Erase method to improve flash EEPROM endurance by combining high voltage source erase and negative gate erase | Jian-Hsing Lee, Kuo-Reay Peng, Ming-Chou Ho | 2000-04-11 |
| 5903499 | Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase | Kuo-Reay Peng, Jian-Hsing Lee, Ming-Chou Ho | 1999-05-11 |
| 5828605 | Snapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROM | Kuo-Reay Peng, Jian-Hsing Lee, Ming-Chon Ho | 1998-10-27 |
| 5726933 | Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROM | Jian-Hsing Lee, Kuo-Reay Peng, Ming-Chou Ho | 1998-03-10 |