Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11545935 | Oscillator wafer-level-package structure | Chih-Hung Chiu, Wun-Kai Wang, HSIANG-JEN CHENG | 2023-01-03 |
| 11398797 | Crystal oscillator and method for fabricating the same | Wun-Kai Wang, Cheng-Wei Lin, Chih-Hung Chiu | 2022-07-26 |
| 9384942 | Specimen preparation for transmission electron microscopy | Yong-Fen Hsieh, Pradeep Sharma, Yu-Feng Ko, Chung-Shi Yang, Lin-Ai Tai +2 more | 2016-07-05 |
| 8969827 | Specimen preparation for transmission electron microscopy | Yong-Fen Hsieh, Pradeep Sharma, Yu-Feng Ko, Chung-Shi Yang, Lin-Ai Tai +1 more | 2015-03-03 |
| 7531438 | Method of fabricating a recess channel transistor | Jih-Wen Chou, Hsiu-Chuan Shu | 2009-05-12 |
| 7462545 | Semicondutor device and manufacturing method thereof | Jih-Wen Chou | 2008-12-09 |
| 6952369 | Method for operating a NAND-array memory module composed of P-type memory cells | Ching-Hsiang Hsu, Ching-Sung Yang, Jih-Wen Chou, Cheng-Tung Huang | 2005-10-04 |
| 6920067 | Integrated circuit embedded with single-poly non-volatile memory | Ching-Hsiang Hsu, Ming-Chou Ho, Shih-Jye Shen | 2005-07-19 |
| 6801456 | Method for programming, erasing and reading a flash memory cell | Ching-Hsiang Hsu, Jih-Wen Chou, Cheng-Tung Huang | 2004-10-05 |
| 6787419 | Method of forming an embedded memory including forming three silicon or polysilicon layers | Chung-Yi Chen, Jih-Wen Chou | 2004-09-07 |
| 6740556 | Method for forming EPROM with low leakage | Ching-Hsiang Hsu, Ming-Chou Ho, Shih-Jye Shen | 2004-05-25 |
| 6617637 | Electrically erasable programmable logic device | Ching-Hsiang Hsu, Yen-Tai Lin, Shih-Jye Shen, Ching-Sung Yang, Ming-Chou Ho | 2003-09-09 |
| 6403411 | Method for manufacturing lower electrode of DRAM capacitor | Horng-Nan Chern, Kevin Lin, Kuo-Tai Huang, Wen-Yi Hsieh, Tri-Rung Yew | 2002-06-11 |
| 6337240 | Method for fabricating an embedded dynamic random access memory | — | 2002-01-08 |
| 6290631 | Method for restoring an alignment mark after planarization of a dielectric layer | Chin-Hung Tseng | 2001-09-18 |
| 6258692 | Method forming shallow trench isolation | Hong-Tsz Pan, Ming-Tzong Yang | 2001-07-10 |
| 6232200 | Method of reconstructing alignment mark during STI process | — | 2001-05-15 |
| 6180493 | Method for forming shallow trench isolation region | — | 2001-01-30 |
| 6127699 | Method for fabricating MOSFET having increased effective gate length | Cheng-Tsung Ni | 2000-10-03 |
| 6114209 | Method of fabricating semiconductor devices with raised doped region structures | Tzu-Jin Yeh | 2000-09-05 |
| 6100126 | Method of making a resistor utilizing a polysilicon plug formed with a high aspect ratio | Min-Liang Chen | 2000-08-08 |
| 6077737 | Method for forming a DRAM having improved capacitor dielectric layers | Ming-Ta Yang | 2000-06-20 |
| 6010944 | Method for increasing capacity of a capacitor | Chi-Dar Huang, Chien-Hung Chen | 2000-01-04 |
| 6008106 | Micro-trench oxidation by using rough oxide mask for field isolation | Tuby Tu, Chen Kuang-Chao, Cheng-Tsung Ni | 1999-12-28 |
| 6001697 | Process for manufacturing semiconductor devices having raised doped regions | A. J. Chang | 1999-12-14 |