Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7897431 | Stacked semiconductor device and method | Hai Zhao | 2011-03-01 |
| 6271556 | High density memory structure | Nan-Hsiung Tsai | 2001-08-07 |
| 6107193 | Completely removal of TiN residue on dual damascence process | G. S. Shiao, Wei-Jing Wen | 2000-08-22 |
| 6100561 | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation | Chih-Hsien Wang | 2000-08-08 |
| 6100126 | Method of making a resistor utilizing a polysilicon plug formed with a high aspect ratio | Chih-Hsun Chu | 2000-08-08 |
| 6020231 | Method for forming LDD CMOS | Chih-Hsien Wang | 2000-02-01 |
| 5972746 | Method for manufacturing semiconductor devices using double-charged implantation | Chih-Hsien Wang, San-Jung Chang, Saysamone Pittikoun | 1999-10-26 |
| 5966632 | Method of forming borderless metal to contact structure | Rebecca Yicksin Tang | 1999-10-12 |
| 5930631 | Method of making double-poly MONOS flash EEPROM cell | Chih-Hsien Wang, Thomas Chang | 1999-07-27 |
| 5926712 | Process for fabricating MOS device having short channel | Chih-Hsien Wang, Chih-Hsun Chu, San-Jung Chang | 1999-07-20 |
| 5885866 | Self-registered cylindrical capacitor of high density DRAMs | — | 1999-03-23 |
| 5880496 | Semiconductor having self-aligned polysilicon electrode layer | Nan-Hsiung Tsai | 1999-03-09 |
| 5827747 | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation | Chih-Hsien Wang | 1998-10-27 |
| 5792686 | Method of forming a bit-line and a capacitor structure in an integrated circuit | Nan-Hsiung Tsai | 1998-08-11 |
| 5789297 | Method of making EEPROM cell device with polyspacer floating gate | Chih-Hsien Wang, Thomas Chang | 1998-08-04 |
| 5703388 | Double-poly monos flash EEPROM cell | Chih-Hsien Wang, Thomas Chang | 1997-12-30 |
| 5691223 | Method of fabricating a capacitor over a bit line DRAM process | Saysamone Pittikoun | 1997-11-25 |
| 5691562 | Through glass ROM code implant to reduce product delivering time | Ying-Kit Tsui, Jau-Nan Kau | 1997-11-25 |
| 5686324 | Process for forming LDD CMOS using large-tilt-angle ion implantation | Chih-Hsien Wang | 1997-11-11 |
| 5681772 | Through glass ROM code implant to reduce product delivering time | Ying-Kit Tsui, Jau-Nan Kau | 1997-10-28 |
| 5679595 | Self-registered capacitor bottom plate-local interconnect scheme for DRAM | Nan-Hsiung Tsai | 1997-10-21 |
| 5625215 | SRAM cell with balanced load resistors | Werner Juengling | 1997-04-29 |
| 5573965 | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology | Sailesh Chittipeddi, Taeho Kook, Richard A. Powell, Pradip K. Roy | 1996-11-12 |
| 5514609 | Through glass ROM code implant to reduce product delivering time | Ying-Kit Tsui, Jau-Nan Kau | 1996-05-07 |
| 5322807 | Method of making thin film transistors including recrystallization and high pressure oxidation | Pradip K. Roy | 1994-06-21 |