Issued Patents All Time
Showing 25 most recent of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8507317 | Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore | Mark A. Bachman, Donald S. Bitting, Seung H. Kang, Sailesh Mansinh Merchant | 2013-08-13 |
| 8030199 | Transistor fabrication method | Taeho Kook, Avinoam Kornblit | 2011-10-04 |
| 7952206 | Solder bump structure for flip chip semiconductor devices and method of manufacture therefore | Mark A. Bachman, Donald S. Bitting, Seung H. Kang, Sailesh Mansinh Merchant | 2011-05-31 |
| 7727894 | Formation of an integrated circuit structure with reduced dishing in metallization levels | Sailesh Mansinh Merchant | 2010-06-01 |
| 7563669 | Integrated circuit with a trench capacitor structure and method of manufacture | Seungmoo Choi | 2009-07-21 |
| 6838769 | Dual damascene bond pad structure for lowering stress and allowing circuitry under pads | William T. Cochran, Yehuda Smooha | 2005-01-04 |
| 6790757 | Wire bonding method for copper interconnects in semiconductor devices | Sailesh Mansinh Merchant | 2004-09-14 |
| 6773994 | CMOS vertical replacement gate (VRG) transistors | Michael J. Kelly | 2004-08-10 |
| 6762087 | Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor | — | 2004-07-13 |
| 6706603 | Method of forming a semiconductor device | — | 2004-03-16 |
| 6628001 | Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same | Keelathur N. Vasudevan | 2003-09-30 |
| 6615195 | Method and system for evaluating technology transfer value | — | 2003-09-02 |
| 6556409 | Integrated circuit including ESD circuits for a multi-chip module and a method therefor | William T. Cochran, Yehuda Smooha | 2003-04-29 |
| 6552381 | Trench capacitors in SOI substrates | Charles Walter Pearce, Pradip K. Roy | 2003-04-22 |
| 6538283 | Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer | Michael J. Kelly | 2003-03-25 |
| 6503793 | Method for concurrently forming an ESD protection device and a shallow trench isolation region | Yehuda Smooha | 2003-01-07 |
| 6500729 | Method for reducing dishing related issues during the formation of shallow trench isolation structures | Arun K. Nanda, Ankineedu Velaga | 2002-12-31 |
| 6498080 | Transistor fabrication method | Taeho Kook, Avinoam Kornblit | 2002-12-24 |
| 6482694 | Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers | Charles Walter Pearce | 2002-11-19 |
| 6472304 | Wire bonding to copper | Sailesh Mansinh Merchant | 2002-10-29 |
| 6455418 | Barrier for copper metallization | Siddhartha Bhowmik, Sailesh Mansinh Merchant | 2002-09-24 |
| 6445043 | Isolated regions in an integrated circuit | — | 2002-09-03 |
| 6426263 | Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain | — | 2002-07-30 |
| 6417087 | Process for forming a dual damascene bond pad structure over active circuitry | William T. Cochran, Yehuda Smooha | 2002-07-09 |
| 6387772 | Method for forming trench capacitors in SOI substrates | Charles Walter Pearce, Pradip K. Roy | 2002-05-14 |