Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6384452 | Electrostatic discharge protection device with monolithically formed resistor-capacitor portion | Yehuda Smooha | 2002-05-07 |
| 6365327 | Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit | Sailesh Mansinh Merchant | 2002-04-02 |
| 6365469 | Method for forming dual-polysilicon structures using a built-in stop layer | Michael J. Kelly | 2002-04-02 |
| 6358785 | Method for forming shallow trench isolation structures | Arun K. Nanda, Ankineedu Velaga | 2002-03-19 |
| 6348393 | Capacitor in an integrated circuit and a method of manufacturing an integrated circuit | Sailesh Mansinh Merchant | 2002-02-19 |
| 6323126 | Tungsten formation process | Arun K. Nanda | 2001-11-27 |
| 6319837 | Technique for reducing dishing in Cu-based interconnects | Sailesh Mansinh Merchant, Pradip K. Roy | 2001-11-20 |
| 6313025 | Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit | Sailesh Mansinh Merchant | 2001-11-06 |
| 6294807 | Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers | Charles Walter Pearce | 2001-09-25 |
| 6288449 | Barrier for copper metallization | Siddhartha Bhowmik, Sailesh Mansinh Merchant | 2001-09-11 |
| 6265890 | In-line non-contact depletion capacitance measurement method and apparatus | Carlos M. Chacon, Pradip K. Roy | 2001-07-24 |
| 6246325 | Distributed communications system for reducing equipment down-time | — | 2001-06-12 |
| 6230293 | Method for quality and reliability assurance testing of integrated circuits using differential Iddq screening in lieu of burn-in | Daryl E. Diehl, Thomas N. Hofacker, Richard Jenkins, Mamata Patnaik, Robert T. Smith +3 more | 2001-05-08 |
| 6207547 | Bond pad design for integrated circuits | Vivian W. Ryan | 2001-03-27 |
| 6191017 | Method of forming a multi-layered dual-polysilicon structure | Michael J. Kelly | 2001-02-20 |
| 6187658 | Bond pad for a flip chip package, and method of forming the same | Vivian W. Ryan | 2001-02-13 |
| 6136620 | Method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein | William T. Cochran, Yehuda Smooha | 2000-10-24 |
| 6136159 | Method for depositing metal | Joseph W. Buckfeller, Sailesh Mansinh Merchant | 2000-10-24 |
| 6087732 | Bond pad for a flip-chip package | Vivian W. Ryan | 2000-07-11 |
| 6080625 | Method for making dual-polysilicon structures in integrated circuits | Michael J. Kelly | 2000-06-27 |
| 6078035 | Integrated circuit processing utilizing microwave radiation | Stephen Knight | 2000-06-20 |
| 6017787 | Integrated circuit with twin tub | William T. Cochran, Stephen Knight | 2000-01-25 |
| 5986343 | Bond pad design for integrated circuits | Vivian W. Ryan | 1999-11-16 |
| 5972179 | Silicon IC contacts using composite TiN barrier layer | Sailesh Mansinh Merchant | 1999-10-26 |
| 5965903 | Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein | William T. Cochran, Yehuda Smooha | 1999-10-12 |