Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6888197 | Power metal oxide semiconductor field effect transistor layout | Jen-Te Chen | 2005-05-03 |
| 6821913 | Method for forming dual oxide layers at bottom of trench | Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng | 2004-11-23 |
| 6784115 | Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities | Jacson Liu, Chih-Sheng Chang, Hudy-Jong Wu | 2004-08-31 |
| 6660592 | Fabricating a DMOS transistor | Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng | 2003-12-09 |
| 6657263 | MOS transistors having dual gates and self-aligned interconnect contact windows | — | 2003-12-02 |
| 6563166 | Flash cell device | — | 2003-05-13 |
| 6284578 | MOS transistors having dual gates and self-aligned interconnect contact windows | — | 2001-09-04 |
| 6228729 | MOS transistors having raised source and drain and interconnects | — | 2001-05-08 |
| 6150244 | Method for fabricating MOS transistor having raised source and drain | — | 2000-11-21 |
| 6127699 | Method for fabricating MOSFET having increased effective gate length | Chih-Hsun Chu | 2000-10-03 |
| 6008106 | Micro-trench oxidation by using rough oxide mask for field isolation | Tuby Tu, Chen Kuang-Chao, Chih-Hsun Chu | 1999-12-28 |
| 5972754 | Method for fabricating MOSFET having increased effective gate length | Chih-Hsun Chu | 1999-10-26 |
| 5804493 | Method for preventing substrate damage during semiconductor fabrication | Minn-Horng Juang, Chih-Hsien Wang | 1998-09-08 |