Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7045435 | Shallow trench isolation method for a semiconductor wafer | — | 2006-05-16 |
| 6784115 | Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities | Cheng-Tsung Ni, Chih-Sheng Chang, Hudy-Jong Wu | 2004-08-31 |
| 6346474 | Dual damascene process | — | 2002-02-12 |
| 6319795 | Method for fabricating VLSI devices having trench isolation regions | — | 2001-11-20 |
| 6245467 | Patterned mask and a deep trench capacitor formed thereby | Hsin-Tang Peng | 2001-06-12 |
| 6218275 | Process for forming self-aligned contact of semiconductor device | Jing Huang | 2001-04-17 |
| 6218267 | Shallow trench isolation method of a semiconductor wafer | — | 2001-04-17 |
| 6146997 | Method for forming self-aligned contact hole | Jing Huang | 2000-11-14 |