Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7521741 | Shielding structures for preventing leakages in high voltage MOS devices | Yu-Chang Jong, Ruey-Hsin Liu, Yueh-Chiou Lin, Shun-Liang Hsu, Te-Yin Hsia | 2009-04-21 |
| 7498653 | Semiconductor structure for isolating integrated circuits of various operating voltages | Chia-Wei Liu, Jun Liu, Tzu-Chiang Sung, Chung-I Chen, Rann-Shyan Yeh | 2009-03-03 |
| 7436043 | N-well and N+ buried layer isolation by auto doping to reduce chip size | Tzu-Chiang Sung, Chih Po Huang, Rann-Shyan Yeh, Jun Liu, Chung-I Chen | 2008-10-14 |
| 7301185 | High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage | Chung-I Chen, Hsin Kuan, Zhi Chen, Rann-Shyan Yeh, Jun Liu +3 more | 2007-11-27 |
| 7253114 | Self-aligned method for defining a semiconductor gate oxide in high voltage device area | Chien-Mao Chen, Jun Liu, Cuker Huang | 2007-08-07 |
| 7205630 | Method and apparatus for a semiconductor device having low and high voltage transistors | Jun Liu, Tsung-Yi Huang, Chung-I Chen, Tzu-Chiang Sung, Chih Po Huang +1 more | 2007-04-17 |
| 7196392 | Semiconductor structure for isolating integrated circuits of various operation voltages | Jun Liu, Tzu-Chiang Sung, Chung-I Chen, Chih Po Huang | 2007-03-27 |