Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11894408 | Dual facing BSI image sensors with wafer level stacking | Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen | 2024-02-06 |
| 11037978 | Dual facing BSI image sensors with wafer level stacking | Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen | 2021-06-15 |
| 10510597 | Methods for hybrid wafer bonding integrated with CMOS processing | Chia-Shiung Tsai, Ping-Yin Liu | 2019-12-17 |
| 10453889 | Dual facing BSI image sensors with wafer level stacking | Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen | 2019-10-22 |
| 9728453 | Methods for hybrid wafer bonding integrated with CMOS processing | Chia-Shiung Tsai, Ping-Yin Liu | 2017-08-08 |
| 9711555 | Dual facing BSI image sensors with wafer level stacking | Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen | 2017-07-18 |
| 6448649 | Multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect | Chung-Kuang Lee | 2002-09-10 |
| 6169314 | Layout pattern for improved MOS device matching | Shyh-Chyi Wong, Jyh-Kang Ting | 2001-01-02 |
| 5952698 | Layout pattern for improved MOS device matching | Shyh-Chyi Wong, Jyh-Kang Ting | 1999-09-14 |
| 5866481 | Selective partial curing of spin-on-glass by ultraviolet radiation to protect integrated circuit dice near the wafer edge | Chia-Shiung Tsai, Sung-Mu Hsu | 1999-02-02 |
| 5801096 | Self-aligned tungsen etch back process to minimize seams in tungsten plugs | Chung-Kuang Lee | 1998-09-01 |
| 5756396 | Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect | Chung-Kuang Lee | 1998-05-26 |
| 5723893 | Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors | Douglas Yu | 1998-03-03 |
| 5712207 | Profile improvement of a metal interconnect structure on a tungsten plug | Chung-Kuang Lee, Pi-Chen Shieh | 1998-01-27 |
| 5702982 | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits | Chung-Kuang Lee, Jung-Hsien Hsu | 1997-12-30 |
| 5575706 | Chemical/mechanical planarization (CMP) apparatus and polish method | Chia-Shiung Tsai | 1996-11-19 |
| 5547881 | Method of forming a resistor for ESD protection in a self aligned silicide process | Jau-Jey Wang, Pi-Chen Shieh | 1996-08-20 |
| 5521121 | Oxygen plasma etch process post contact layer etch back | Chia-Shiun Tsai, Jiunn-Wen Weng | 1996-05-28 |
| 5411907 | Capping free metal silicide integrated process | Chue-San Yoo, Jyh-Min Tsaur, Chong-Shi Chen | 1995-05-02 |