Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11984483 | Semiconductor device and method of manufacturing thereof | — | 2024-05-14 |
| 11616131 | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate | Tai-Hsin Chiu | 2023-03-28 |
| 11150680 | Two-transistor bandgap reference circuit and FinFET device suited for same | Yvonne Lin, Da-Wen Lin, Peter Huang, Paul Rousseau | 2021-10-19 |
| 10534393 | Two-transistor bandgap reference circuit and FinFET device suited for same | Yvonne Lin, Da-Wen Lin, Peter Huang, Paul Rousseau | 2020-01-14 |
| 10522643 | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate | Tai-Hsin Chiu | 2019-12-31 |
| 10466731 | Two-transistor bandgap reference circuit and FinFET device suited for same | Yvonne Lin, Da-Wen Lin, Peter Huang, Paul Rousseau | 2019-11-05 |
| 9385213 | Integrated circuits and manufacturing methods thereof | Chung-Cheng Wu, Ali Keshavarzi, Ka-Hing Fung, Ta-Pen Guo, Jiann-Tyng Tzeng +6 more | 2016-07-05 |
| 8389316 | Strain bars in stressed layers of MOS devices | Yen-Sen Wang, Chung-Te Lin, Min Cao | 2013-03-05 |
| 8362573 | Integrated circuits and manufacturing methods thereof | Chung-Cheng Wu, Ali Keshavarzi, Ka-Hing Fung, Ta-Pen Guo, Jiann-Tyng Tzeng +6 more | 2013-01-29 |
| 8350330 | Dummy pattern design for reducing device performance drift | Lee-Chung Lu, Chien-Chih Kuo, Jian-Yi Li | 2013-01-08 |
| 7958465 | Dummy pattern design for reducing device performance drift | Lee-Chung Lu, Chien-Chih Kuo, Jian-Yi Li | 2011-06-07 |
| 7943961 | Strain bars in stressed layers of MOS devices | Yen-Sen Wang, Chung-Te Lin, Min Cao | 2011-05-17 |
| 7598130 | Method for reducing layout-dependent variations in semiconductor devices | Chung-Heng Yang, Yi-Ming Sheu | 2009-10-06 |