Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5924011 | Silicide process for mixed mode product | — | 1999-07-13 |
| 5918120 | Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines | — | 1999-06-29 |
| 5918119 | Process for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structure | — | 1999-06-29 |
| 5899722 | Method of forming dual spacer for self aligned contact integration | — | 1999-05-04 |
| 5872030 | Method of improving beta ratio in SRAM and device manufactured thereby | — | 1999-02-16 |
| 5863820 | Integration of sac and salicide processes on a chip having embedded memory | — | 1999-01-26 |
| 5854119 | Robust method of forming a cylinder capacitor for DRAM circuits | James Wu, Yu-Hua Lee | 1998-12-29 |
| 5834811 | Salicide process for FETs | — | 1998-11-10 |
| 5828111 | Increase resistance of a polysilicon load resistor, in an SRAM cell | Yi-Miaw Lin | 1998-10-27 |
| 5821141 | Method for forming a cylindrical capacitor in DRAM having pin plug profile | — | 1998-10-13 |
| 5726932 | Trench free SRAM cell structure | Jin-Yuan Lee, Ming-Chih Chung | 1998-03-10 |
| 5721166 | Method to increase the resistance of a polysilicon load resistor, in an SRAM cell | Yi-Miaw Lin | 1998-02-24 |
| 5646057 | Method for a MOS device manufacturing | Chwen-Ming Liu, Hsien-Wei Chin, Huan-Chung You, Jang-Cheng Hsieh | 1997-07-08 |
| 5607881 | Method of reducing buried contact resistance in SRAM | — | 1997-03-04 |
| 5596215 | Method to improve buried contact resistance | — | 1997-01-21 |
| 5554549 | Salicide process for FETs | — | 1996-09-10 |
| 5525552 | Method for fabricating a MOSFET device with a buried contact | — | 1996-06-11 |
| 5494843 | Method for forming MOSFET devices | — | 1996-02-27 |