Issued Patents All Time
Showing 25 most recent of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8309457 | Multilayer low reflectivity hard mask and process therefor | Kouros Ghandehari, Anna M. Minvielle, Hirokazu Tokuno | 2012-11-13 |
| 8048797 | Multilayer low reflectivity hard mask and process therefor | Kouros Ghandehari, Anna M. Minvielle, Hirokazu Tokuno | 2011-11-01 |
| 7964905 | Anti-reflective interpoly dielectric | Robert B. Ogle, Mark T. Ramsbey | 2011-06-21 |
| 7659166 | Integration approach to form the core floating gate for flash memory using an amorphous carbon hard mask and ArF lithography | Scott A. Bell | 2010-02-09 |
| 7538026 | Multilayer low reflectivity hard mask and process therefor | Kouros Ghandehari, Anna M. Minvielle, Hirokazu Tokuno | 2009-05-26 |
| 7427457 | Methods for designing grating structures for use in situ scatterometry to detect photoresist defects | Calvin T. Gabriel, Christopher F. Lyons, Anna M. Minvielle | 2008-09-23 |
| 7368225 | Two mask photoresist exposure pattern for dense and isolated regions | Ramkumar Subramanian, Scott A. Bell, Todd P. Lukanc, Uzodinma Okoroanyanwu, Hung-Eil Kim | 2008-05-06 |
| 7268066 | Method for semiconductor gate line dimension reduction | Douglas J. Bonser, Chih-Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher +1 more | 2007-09-11 |
| 7122455 | Patterning with rigid organic under-layer | Christopher F. Lyons, Srikanteswara Dakshina-Murthy, Scott A. Bell, Cyrus E. Tabery | 2006-10-17 |
| 7112489 | Negative resist or dry develop process for forming middle of line implant layer | Christopher F. Lyons, Anna M. Minvielle | 2006-09-26 |
| 7052921 | System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process | Bhanwar Singh, Calvin T. Gabriel, Christopher F. Lyons, Scott A. Bell, Ramkumar Subramanian +1 more | 2006-05-30 |
| 7018922 | Patterning for elongated VSS contact flash memory | Hung-Eil Kim, Anna M. Minvielle, Christopher F. Lyons, Ramkumar Subramanian | 2006-03-28 |
| 7015134 | Method for reducing anti-reflective coating layer removal during removal of photoresist | Angela T. Hui | 2006-03-21 |
| 7008832 | Damascene process for a T-shaped gate electrode | Ramkumar Subramanian, Christopher F. Lyons, Bhanwar Singh | 2006-03-07 |
| 6913958 | Method for patterning a feature using a trimmed hardmask | Marilyn I. Wright, Chih-Yuh Yang, Douglas J. Bonser | 2005-07-05 |
| 6900124 | Patterning for elliptical Vss contact on flash memory | Hung-Eil Kim, Anna M. Minvielle, Christopher F. Lyons, Ramkumar Subramanian | 2005-05-31 |
| 6900002 | Antireflective bi-layer hardmask including a densified amorphous carbon layer | Marilyn I. Wright, Lu You, Scott A. Bell | 2005-05-31 |
| 6869888 | E-beam flood exposure of spin-on material to eliminate voids in vias | Ramkumar Subramanian, Christopher F. Lyons, Bhanwar Singh | 2005-03-22 |
| 6867097 | Method of making a memory cell with polished insulator layer | Mark T. Ramsbey, Robert B. Ogle, Tommy Hsiao, Angela T. Hui, Tuan Pham +1 more | 2005-03-15 |
| 6864556 | CVD organic polymer film for advanced gate patterning | Lu You, Chih-Yuh Yang, Scott A. Bell, Richard J. Huang, Christopher F. Lyons +2 more | 2005-03-08 |
| 6849530 | Method for semiconductor gate line dimension reduction | Douglas J. Bonser, Chih-Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher +1 more | 2005-02-01 |
| 6828259 | Enhanced transistor gate using E-beam radiation | Philip A. Fisher, Chih-Yuh Yang, Russell R.A. Callahan, Ashok M. Khathuria | 2004-12-07 |
| 6818141 | Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines | Kouros Ghandehari | 2004-11-16 |
| 6803178 | Two mask photoresist exposure pattern for dense and isolated regions | Ramkumar Subramanian, Scott A. Bell, Todd P. Lukanc, Uzodinma Okoroanyanwu, Hung-Eli Kim | 2004-10-12 |
| 6797552 | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices | Mark S. Chang, Douglas J. Bonser, Chih-Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy | 2004-09-28 |