Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6403456 | T or T/Y gate formation using trim etch processing | Christopher F. Lyons, Bhanwar Singh, Ramkumar Subramanian | 2002-06-11 |
| 6383952 | RELACS process to double the frequency or pitch of small feature formation | Ramkumar Subramanian, Bhanwar Singh, Christopher F. Lyons, Scott A. Bell | 2002-05-07 |
| 6365509 | Semiconductor manufacturing method using a dielectric photomask | Ramkumar Subramanian, Wenge Yang, Lewis Shen | 2002-04-02 |
| 6358856 | Bright field image reversal for contact hole patterning | Christopher F. Lyons, Ramkumar Subramanian, Todd P. Lukanc | 2002-03-19 |
| 6326231 | Use of silicon oxynitride ARC for metal layers | Ramkumar Subramanian, Bhanwar Singh, Sanjay K. Yedur, Christopher F. Lyons, Bharath Rangarajan +1 more | 2001-12-04 |
| 6319802 | T-gate formation using modified damascene processing with two masks | Ramkumar Subramanian, Christopher F. Lyons, Bhanwar Singh | 2001-11-20 |
| 6313019 | Y-gate formation using damascene processing | Ramkumar Subramanian, Christopher F. Lyons, Bhanwar Singh | 2001-11-06 |
| 6306769 | Use of dual patterning masks for printing holes of small dimensions | Ramkumar Subramanian | 2001-10-23 |
| 6270929 | Damascene T-gate using a relacs flow | Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh | 2001-08-07 |
| 6265751 | Method and system for reducing ARC layer removal by condensing the ARC layer | Robert B. Ogle | 2001-07-24 |
| 6262435 | Etch bias distribution across semiconductor wafer | Luigi Capodieci, Scott A. Bell, Todd P. Lukanc | 2001-07-17 |
| 6255202 | Damascene T-gate using a spacer flow | Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh | 2001-07-03 |
| 6255125 | Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer | Regina Tien Schmidt, Christopher A. Spence, Anna M. Minvielle, Khanh B. Nguyen | 2001-07-03 |
| 6222241 | Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer | — | 2001-04-24 |
| 6210050 | Resist developing method and apparatus with nozzle offset for uniform developer application | Christopher F. Lyons | 2001-04-03 |
| 6187687 | Minimization of line width variation in photolithography | Ming-Yin Hao | 2001-02-13 |
| 6057206 | Mark protection scheme with no masking | Khanh B. Nguyen, Christopher F. Lyons, Harry J. Levinson | 2000-05-02 |
| 5821036 | Method of developing positive photoresist and compositions therefor | Stanley A. Ficner, John Magvas, Christopher F. Lyons, Wayne M. Moreau | 1998-10-13 |