Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Luigi Capodieci — 44 Patents

AMD: 30 patents #326 of 9,280Top 4%
Globalfoundries: 11 patents #330 of 4,424Top 8%
ABAsm Lithography B.V.: 1 patents #15 of 53Top 30%
ABAsml Masktools B.V.: 1 patents #29 of 37Top 80%
Madison, WI: #50 of 4,527 inventorsTop 2%
Wisconsin: #507 of 40,088 inventorsTop 2%
Overall (All Time): #66,838 of 4,157,543Top 2%
44 Patents All Time
Luigi Capodieci has been granted 44 US patents while listed as an inventor at AMD. The first was granted in 1998 and the most recent in December 2014. Luigi Capodieci ranks #66,838 of 4,157,543 US inventors in our database (top 1.6%). Patent records list Luigi Capodieci in Madison, WI, US.

Patents per Year

Patents granted per year, 1998 to 2014Bar chart with a peak of 8 patents in 2007.peak 81998: 1 patents19982000: 5 patents2001: 3 patents20012002: 2 patents2003: 3 patents20032005: 2 patents2006: 5 patents20062007: 8 patents2008: 1 patents20082009: 1 patents2010: 3 patents20102012: 2 patents2013: 4 patents20132014: 4 patents2014

Issued Patents All Time

Showing 1–25 of 44 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8924896 Automated design layout pattern correction based on context-aware patterns Lynn Wang, Vito Dai 2014-12-30 $1,485,000
8918745 Stitch insertion for reducing color density differences in double patterning technology (DPT) Lynn Wang, Sriram Madhavan 2014-12-23 $2,667,000
8910090 Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications Lynn Wang, Vito Dai 2014-12-09 $981,000
8898606 Layout pattern correction for integrated circuits Rani S. Abou Ghaida, Ahmed Mohyeldin, Piyush Pathak, Swamy Muddu, Vito Dai 2014-11-25 $6,684,000
8589844 Methods for analyzing design rules Swamy Muddu, Abde Ali Hunaid Kagalwalla 2013-11-19 $2,505,000
8555215 Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns Yi Zou, Swamy Maddu, Lynn Wang, Vito Dai, Peng Xie 2013-10-08 $4,437,000
8516407 Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts Lynn Wang, Sriram Madhavan 2013-08-20 $3,491,000
8418105 Methods for pattern matching in a double patterning technology-compliant physical design flow Lynn Wang, Vito Dai 2013-04-09 $4,395,000
8124300 Method of lithographic mask correction using localized transmission adjustment Bhanwar Singh 2012-02-28 $5,561,000
8103979 System for generating and optimizing mask assist features based on hybrid (model and rules) methodology Yi Zou 2012-01-24 $3,915,000
7799517 Single/double dipole mask for contact holes 2010-09-21 $7,003,000
7757190 Design rules checking augmented with pattern matching Vito Dai, Jie Yang, Norma C. Rodriguez 2010-07-13 $9,965,000
7657864 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques Cyrus E. Tabery, Todd P. Lukanc, Chris Haidinyak, Carl P. Babcock, Hung-Eil Kim +1 more 2010-02-02 $18,664,000
7543256 System and method for designing an integrated circuit device Todd P. Lukanc, Cyrus E. Tabery, Carl P. Babcock, Hung-Eil Kim, Christopher A. Spence +1 more 2009-06-02 $11,563,000
7354682 Chromeless mask for contact holes 2008-04-08 $4,787,000
7313777 Layout verification based on probability of printing fault Jie Yang 2007-12-25
7313769 Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin Todd P. Lukanc, Cyrus E. Tabery, Carl P. Babcock, Hung-Eil Kim, Christopher A. Spence +1 more 2007-12-25
7310155 Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures Amit P. Marathe, Bhanwar Singh, Ramkumar Subramanian 2007-12-18 $12,803,000
7305645 Method for manufacturing place & route based on 2-D forbidden patterns Bhanwar Singh, Ramkumar Subramanian 2007-12-04
7269804 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques Cyrus E. Tabery, Todd P. Lukanc, Chris Haidinyak, Carl P. Babcock, Hung-Eil Kim +1 more 2007-09-11 $10,117,000
7263683 Simplified optical proximity correction based on 1-dimension versus 2-dimension pattern shape classification 2007-08-28 $7,142,000
7207017 Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results Cyrus E. Tabery, Chris Haidinyak, Todd P. Lukanc, Carl P. Babcock, Hung-Eil Kim +1 more 2007-04-17 $14,172,000
7194725 System and method for design rule creation and selection Todd P. Lukanc, Cyrus E. Tabery, Carl P. Babcock, Hung-Eil Kim, Christopher A. Spence +1 more 2007-03-20 $9,786,000
7080349 Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing Carl P. Babcock 2006-07-18 $7,111,000
7071085 Predefined critical spaces in IC patterning to reduce line end pull back Todd P. Lukanc, Christopher A. Spence, Joerg Reiss, Sarah N. McGowan 2006-07-04