Issued Patents All Time
Showing 25 most recent of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9905552 | Assist cuts disposed in dummy lines to improve metal signal cuts in active lines of a semiconductor structure | Lei Yuan, Xuelian Zhu | 2018-02-27 |
| 9798852 | Methods of design rule checking of circuit designs | Lei Yuan, Jongwook Kye | 2017-10-24 |
| 9613177 | Methods of generating circuit layouts that are to be manufactured using SADP routing techniques | Lei Yuan, Soo Han Choi, Jongwook Kye | 2017-04-04 |
| 9547232 | Pellicle with aerogel support frame | Obert R. Wood, II | 2017-01-17 |
| 9536778 | Self-aligned double patterning process for metal routing | Lei Yuan, Jongwook Kye | 2017-01-03 |
| 9437588 | Middle of-line architecture for dense library layout using M0 hand-shake | Jia Zeng, Jongwook Kye | 2016-09-06 |
| 9431300 | MOL architecture enabling ultra-regular cross couple | Jia Zeng, Jongwook Kye | 2016-08-30 |
| 9330221 | Mask-aware routing and resulting device | Lei Yuan, Jongwook Kye | 2016-05-03 |
| 9287131 | Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules | Lei Yuan, Jongwook Kye | 2016-03-15 |
| 9147653 | Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology | Lei Yuan, Jongwook Kye | 2015-09-29 |
| 9093481 | Method for semiconductor wafer fabrication utilizing a cleaning substrate | — | 2015-07-28 |
| 8966412 | Methods of generating circuit layouts that are to be manufactured using SADP techniques | Lei Yuan, Jongwook Kye | 2015-02-24 |
| 8954913 | Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules | Lei Yuan, Soo Han Choi, Jongwook Kye | 2015-02-10 |
| 8921225 | Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology | Lei Yuan, Jongwook Kye | 2014-12-30 |
| 8918746 | Cut mask aware contact enclosure rule for grating and cut patterning solution | Lei Yuan, Jongwook Kye | 2014-12-23 |
| 8843869 | Via insertion in integrated circuit (IC) designs | Lei Yuan, Jongwook Kye | 2014-09-23 |
| 8839168 | Self-aligned double patterning via enclosure design | Jongwook Kye, Jason E. Stephens, Lei Yuan | 2014-09-16 |
| 8815748 | Method of forming semiconductor device with multiple level patterning | Thomas I. Wallow, Ryoung-Han Kim, Jongwook Kye | 2014-08-26 |
| 8809184 | Methods of forming contacts for semiconductor devices using a local interconnect processing scheme | Lei Yuan, Jin Cho, Jongwook Kye | 2014-08-19 |
| 8792161 | Optical polarizer with nanotube array | Bruno M. LaFontaine, Ryoung-Han Kim, Uzodinma Okoroanyanwu | 2014-07-29 |
| 8741763 | Layout designs with via routing structures | Yuansheng Ma, Jongwook Kye, Hidekazu Yoshida, Mahbub Rashed | 2014-06-03 |
| 8586269 | Method for forming a high resolution resist pattern on a semiconductor wafer | Uzodinma Okoroanyanwu, Ryoung-Han Kim, Thomas I. Wallow | 2013-11-19 |
| 8367430 | Shape characterization with elliptic fourier descriptor for contact or any closed structures on the chip | Yuansheng Ma, Jongwook Kye | 2013-02-05 |
| 8338061 | Fluorine-passivated reticles for use in lithography and methods for fabricating the same | Uzodinma Okoroanyanwu, Anna Tchikoulaeva, Rene Wirtz | 2012-12-25 |
| 8324106 | Methods for fabricating a photolithographic mask and for fabricating a semiconductor integrated circuit using such a mask | Lei Yuan, Jongwook Kye | 2012-12-04 |