Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12032894 | System and method for synchronizing net text across hierarchical levels | Louis Schaffer, Kenter Lin | 2024-07-09 |
| 11972191 | System and method for providing enhanced net pruning | Louis Schaffer, Timmy Lin | 2024-04-30 |
| 10261412 | Categorized stitching guidance for triple-patterning technology | Srini Arikati, Erdem Cilingir | 2019-04-16 |
| 9747407 | Categorized stitching guidance for triple-patterning technology | Srini Arikati, Erdem Cilingir | 2017-08-29 |
| 9613177 | Methods of generating circuit layouts that are to be manufactured using SADP routing techniques | Lei Yuan, Jongwook Kye, Harry J. Levinson | 2017-04-04 |
| 9400863 | Color-insensitive rules for routing structures | Lei Yuan, Li Yang, Jongwook Kye | 2016-07-26 |
| 9158879 | Color-insensitive rules for routing structures | Lei Yuan, Li Yang, Jongwook Kye | 2015-10-13 |
| 9141751 | Method of forming a pattern | Hyun Jong Lee, Jung-Ho Do, Chul-Hong Park, Sang-Pil Sim | 2015-09-22 |
| 8969199 | Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process | Lei Yuan, Jason E. Stephens, Li Yang | 2015-03-03 |
| 8954913 | Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules | Lei Yuan, Jongwook Kye, Harry J. Levinson | 2015-02-10 |
| 8045787 | System for analyzing mask topography and method of forming image using the system | Yong-jin Chun, Moon-Hyun Yoo, Joon-Ho Choi, Ji Suk Hong | 2011-10-25 |
| 7361435 | Method of creating a layout of a set of masks | Chul-Hong Park, Moon-Hyun Yoo, Yoo H. Kim, Dong Hyun Kim | 2008-04-22 |
| 7097949 | Phase edge phase shift mask enforcing a width of a field gate image and fabrication method thereof | Dong Hyun Kim, Moon-Hyun Yoo, Jeong-Lim Nam, Yoo H. Kim, Chul-Hong Park +2 more | 2006-08-29 |
| 6998199 | Mask for manufacturing a highly-integrated circuit device | Chul-Hong Park, Moon-Hyun Yoo, Yoo H. Kim, Dong Hyun Kim | 2006-02-14 |
| 5827571 | Hot-wall CVD method for forming a ferroelectric film | Seaung Suk Lee, Ho Gi Kim, Jong Choul Kim | 1998-10-27 |
| 5710735 | EEPROM and method for fabricating the same | Ki Soo Shin | 1998-01-20 |
| 5614429 | Method for fabricating EEPROM with control gate in touch with select gate | Ki Soo Shin | 1997-03-25 |