| 12457799 |
Antenna structure |
Xuemei Zhu, Navneet Jain, Junegeol Kim, James P. Mazza, Jihui Zeng +1 more |
2025-10-28 |
|
| 12438078 |
Local interconnect power rails and upper power rails |
James P. Mazza, Navneet Jain, Xuemei Zhu, Jihui Zeng |
2025-10-07 |
|
| 12288782 |
Cell layouts |
Juhan Kim, Sangmoon Kim, Navneet Jain |
2025-04-29 |
|
| 12272299 |
Compact memory-in-pixel display structure |
Juhan Kim, Sanjay R. Parihar, Zahir Y. Alpaslan |
2025-04-08 |
|
| 12260163 |
System and method employing power-optimized timing closure |
Navneet Jain |
2025-03-25 |
|
| 12183394 |
Circuit structure and related method for radiation resistant memory cell |
Vivek Raj, Shivraj G. Dharne |
2024-12-31 |
$107,052,000 |
| 12148702 |
Semiconductor device with transistor local interconnects |
Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more |
2024-11-19 |
$68,003,000 |
| 12050485 |
Post-manufacture latch timing control blocks in pipelined processors |
Vivek Raj, Sunil Kumar, Shivraj G. Dharne |
2024-07-30 |
$38,673,000 |
| 12046603 |
Semiconductor structure including sectioned well region |
Navneet Jain, Nigel Chan |
2024-07-23 |
$41,882,000 |
| 11979145 |
Back bias control for always-on circuit section enabling leakage reduction during power saving mode |
Navneet Jain |
2024-05-07 |
$71,725,000 |
| 11929399 |
Deep nwell contact structures |
Navneet Jain |
2024-03-12 |
$70,746,000 |
| 11894845 |
Structure and method for delaying of data signal from pulse latch with lockup latch |
Navneet Jain |
2024-02-06 |
$79,208,000 |
| 11862240 |
Circuit structure and related method for radiation resistant memory cell |
Vivek Raj, Shivraj G. Dharne |
2024-01-02 |
$58,072,000 |
| 11495288 |
Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method |
Vivek Raj, Shivraj G. Dharne, Uttam Saha |
2022-11-08 |
$136,033,000 |
| 11444031 |
Semiconductor device with transistor local interconnects |
Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more |
2022-09-13 |
$109,884,000 |
| 11322200 |
Single-rail memory circuit with row-specific voltage supply lines and boost circuits |
Vivek Raj, Shivraj G. Dharne, Uttam Saha |
2022-05-03 |
$45,675,000 |
| 11218137 |
Low clock load dynamic dual output latch circuit |
Uttam Saha |
2022-01-04 |
$58,261,000 |
| 11050414 |
Dynamic single input-dual output latch |
Uttam Saha |
2021-06-29 |
|
| 10833018 |
Semiconductor device with transistor local interconnects |
Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more |
2020-11-10 |
$61,528,000 |
| 10819110 |
Electrostatic discharge protection device |
Anil Kumar, Manjunatha Prabhu, Alain Loiseau, Sushama Davar |
2020-10-27 |
$44,640,000 |
| 10678287 |
Positive and negative full-range back-bias generator circuit structure |
Arif A. Siddiqi, Juhan Kim |
2020-06-09 |
$60,273,000 |
| 10658294 |
Structure and method for flexible power staple insertion |
Juhan Kim, Navneet Jain |
2020-05-19 |
$54,061,000 |
| 10366954 |
Structure and method for flexible power staple insertion |
Juhan Kim, Navneet Jain |
2019-07-30 |
$35,149,000 |
| 10360334 |
Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library |
Navneet Jain, Juhan Kim |
2019-07-23 |
$90,834,000 |
| 10347543 |
FDSOI semiconductor device with contact enhancement layer and method of manufacturing |
Peter Baars, Rick Carter, Vikrant Chauhan, George Jonathan Kluth, Anurag Mittal +1 more |
2019-07-09 |
$33,274,000 |
