Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12288782 | Cell layouts | Juhan Kim, Sangmoon Kim, Navneet Jain | 2025-04-29 |
| 12272299 | Compact memory-in-pixel display structure | Juhan Kim, Sanjay R. Parihar, Zahir Y. Alpaslan | 2025-04-08 |
| 12260163 | System and method employing power-optimized timing closure | Navneet Jain | 2025-03-25 |
| 12183394 | Circuit structure and related method for radiation resistant memory cell | Vivek Raj, Shivraj G. Dharne | 2024-12-31 |
| 12148702 | Semiconductor device with transistor local interconnects | Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2024-11-19 |
| 12050485 | Post-manufacture latch timing control blocks in pipelined processors | Vivek Raj, Sunil Kumar, Shivraj G. Dharne | 2024-07-30 |
| 12046603 | Semiconductor structure including sectioned well region | Navneet Jain, Nigel Chan | 2024-07-23 |
| 11979145 | Back bias control for always-on circuit section enabling leakage reduction during power saving mode | Navneet Jain | 2024-05-07 |
| 11929399 | Deep nwell contact structures | Navneet Jain | 2024-03-12 |
| 11894845 | Structure and method for delaying of data signal from pulse latch with lockup latch | Navneet Jain | 2024-02-06 |
| 11862240 | Circuit structure and related method for radiation resistant memory cell | Vivek Raj, Shivraj G. Dharne | 2024-01-02 |
| 11495288 | Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method | Vivek Raj, Shivraj G. Dharne, Uttam Saha | 2022-11-08 |
| 11444031 | Semiconductor device with transistor local interconnects | Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2022-09-13 |
| 11322200 | Single-rail memory circuit with row-specific voltage supply lines and boost circuits | Vivek Raj, Shivraj G. Dharne, Uttam Saha | 2022-05-03 |
| 11218137 | Low clock load dynamic dual output latch circuit | Uttam Saha | 2022-01-04 |
| 11050414 | Dynamic single input-dual output latch | Uttam Saha | 2021-06-29 |
| 10833018 | Semiconductor device with transistor local interconnects | Irene Y. Lin, Steven R. Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2020-11-10 |
| 10819110 | Electrostatic discharge protection device | Anil Kumar, Manjunatha Prabhu, Alain Loiseau, Sushama Davar | 2020-10-27 |
| 10678287 | Positive and negative full-range back-bias generator circuit structure | Arif A. Siddiqi, Juhan Kim | 2020-06-09 |
| 10658294 | Structure and method for flexible power staple insertion | Juhan Kim, Navneet Jain | 2020-05-19 |
| 10366954 | Structure and method for flexible power staple insertion | Juhan Kim, Navneet Jain | 2019-07-30 |
| 10360334 | Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library | Navneet Jain, Juhan Kim | 2019-07-23 |
| 10347543 | FDSOI semiconductor device with contact enhancement layer and method of manufacturing | Peter Baars, Rick Carter, Vikrant Chauhan, George Jonathan Kluth, Anurag Mittal +1 more | 2019-07-09 |
| 10340288 | Method, apparatus, and system for improved memory cell design having unidirectional layout using self-aligned double patterning | Juhan Kim | 2019-07-02 |
| 10333497 | Calibration devices for I/O driver circuits having switches biased differently for different temperatures | Anil Kumar, Sushama Davar, Navneet Jain | 2019-06-25 |