Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148702 | Semiconductor device with transistor local interconnects | Mahbub Rashed, Irene Y. Lin, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2024-11-19 |
| 11475941 | Non-volatile transistor embedded static random access memory (SRAM) cell | Akhilesh Jaiswal, Bipul C. Paul | 2022-10-18 |
| 11444031 | Semiconductor device with transistor local interconnects | Mahbub Rashed, Irene Y. Lin, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2022-09-13 |
| 11349071 | Memory device and a method for forming the memory device | Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan | 2022-05-31 |
| 11315949 | Charge-trapping sidewall spacer-type non-volatile memory device and method | Tom Herrmann, Leitao Liu, Alban Zaka | 2022-04-26 |
| 11217533 | Semiconductor device with metal structure under an active layer | Steven Bentley, Julien Frougier | 2022-01-04 |
| 11201152 | Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor | Ruilong Xie, Steven Bentley, Daniel Chanemougame, Julien Frougier, Bipul C. Paul +1 more | 2021-12-14 |
| 11145348 | Circuit structure and method for memory storage with memory cell and MRAM stack | Akhilesh Jaiswal, Ajey Poovannummoottil Jacob | 2021-10-12 |
| 11101348 | Nanosheet field effect transistor with spacers between sheets | Ruilong Xie, Julien Frougier, Nigel G. Cave, Daniel Chanemougame, Steven Bentley +2 more | 2021-08-24 |
| 11004509 | Circuit structure and memory circuit with resistive memory elements, and related methods | Bipul C. Paul | 2021-05-11 |
| 10964367 | MRAM device comprising random access memory (RAM) and embedded read only memory (ROM) | Akhilesh Jaiswal, Ajey Poovannummoottil Jacob | 2021-03-30 |
| 10833018 | Semiconductor device with transistor local interconnects | Mahbub Rashed, Irene Y. Lin, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2020-11-10 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Ruilong Xie, Chanro Park, Daniel Chanemougame, Lars Liebmann, Hui Zang +1 more | 2020-06-30 |
| 10658243 | Method for forming replacement metal gate and related structures | Ruilong Xie, Daniel Chanemougame, Steven Bentley, Chanro Park | 2020-05-19 |
| 10629500 | Product that includes a plurality of vertical transistors with a shared conductive gate plug | Steven Bentley | 2020-04-21 |
| 10559686 | Methods of forming gate contact over active region for vertical FinFET, and structures formed thereby | Ruilong Xie, Hui Zang | 2020-02-11 |
| 10510620 | Work function metal patterning for N-P space between active nanostructures | Daniel Chanemougame, Steven Bentley, Julien Frougier, Ruilong Xie | 2019-12-17 |
| 10446451 | Method for forming replacement gate structures for vertical transistors | Steven Bentley | 2019-10-15 |
| 10418368 | Buried local interconnect in source/drain region | Steven Bentley, Bipul C. Paul | 2019-09-17 |
| 10332803 | Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming | Ruilong Xie, Edward J. Nowak, Bipul C. Paul, Julien Frougier, Daniel Chanemougame +1 more | 2019-06-25 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Hui Zang +8 more | 2019-02-26 |
| 9625557 | Work function calibration of a non-contact voltage sensor | M. Brandon Steele | 2017-04-18 |
| 9355910 | Semiconductor device with transistor local interconnects | Mahbub Rashed, Irene Y. Lin, Jeff Kim, Chinh Nguyen, Marc Tarabbia +3 more | 2016-05-31 |
| 9048171 | Method to dynamically tune precision resistance | Andreas Knorr | 2015-06-02 |
| 8940634 | Overlapping contacts for semiconductor device | Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Jin Z. Wallner | 2015-01-27 |