SB

Steven Bentley

Globalfoundries: 69 patents #26 of 4,424Top 1%
GU Globalfoundries U.S.: 10 patents #60 of 665Top 10%
IBM: 6 patents #16,453 of 70,183Top 25%
RE Renesas Electronics: 4 patents #1,016 of 4,529Top 25%
NT Niab Trading: 1 patents #2 of 2Top 100%
Overall (All Time): #22,080 of 4,157,543Top 1%
81
Patents All Time

Issued Patents All Time

Showing 25 most recent of 81 patents

Patent #TitleCo-InventorsDate
12416530 Temperature detection using negative temperature coefficient resistor in GaN setting Santosh Sharma, Michael J. Zierak, Johnatan A. Kantarovsky 2025-09-16
12417975 Electrically programmable fuse over crystalline semiconductor materials Johnatan A. Kantarovsky, Santosh Sharma, Michael J. Zierak, Ephrem G. Gebreselasie 2025-09-16
12183814 Multi-channel transistor Francois Hebert, Lawrence Selvaraj Susai, Johnatan A. Kantarovsky, Michael J. Zierak, Mark D. Levy +1 more 2024-12-31
11616127 Symmetric arrangement of field plates in semiconductor devices Johnatan A. Kantarovsky, Rajendran Krishnasamy, Siva P. Adusumilli, Michael J. Zierak, Jeonghyun Hwang 2023-03-28
11569170 Substrate with a buried conductor under an active region for enhanced thermal conductivity and RF shielding Siva P. Adusumilli, Mark D. Levy, Ramsey Hazbun, Alvin J. Joseph 2023-01-31
11515397 III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer Anthony K. Stamper, Siva P. Adusumilli, Vibhor Jain 2022-11-29
11316019 Symmetric arrangement of field plates in semiconductor devices Johnatan A. Kantarovsky, Rajendran Krishnasamy, Siva P. Adusumilli, Michael J. Zierak, Jeonghyun Hwang 2022-04-26
11217533 Semiconductor device with metal structure under an active layer Steven R. Soss, Julien Frougier 2022-01-04
11201152 Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor Ruilong Xie, Steven R. Soss, Daniel Chanemougame, Julien Frougier, Bipul C. Paul +1 more 2021-12-14
11195761 IC structure with short channel gate structure having shorter gate height than long channel gate structure Haiting Wang, Hong Yu 2021-12-07
11101348 Nanosheet field effect transistor with spacers between sheets Ruilong Xie, Julien Frougier, Nigel G. Cave, Steven R. Soss, Daniel Chanemougame +2 more 2021-08-24
10797138 Vertical-transport field-effect transistors with self-aligned contacts Emilie Bourjot, Daniel Chanemougame 2020-10-06
10685847 Vertical nanowires formed on upper fin surface Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob 2020-06-16
10658243 Method for forming replacement metal gate and related structures Ruilong Xie, Daniel Chanemougame, Steven R. Soss, Chanro Park 2020-05-19
10629500 Product that includes a plurality of vertical transistors with a shared conductive gate plug Steven R. Soss 2020-04-21
10510620 Work function metal patterning for N-P space between active nanostructures Daniel Chanemougame, Steven R. Soss, Julien Frougier, Ruilong Xie 2019-12-17
10497798 Vertical field effect transistor with self-aligned contacts Ruilong Xie, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann +2 more 2019-12-03
10475904 Methods of forming merged source/drain regions on integrated circuit products Hiroaki Niimi, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian 2019-11-12
10461196 Control of length in gate region during processing of VFET structures Chanro Park, Ruilong Xie, Min Gyu Sung 2019-10-29
10446659 Negative capacitance integration through a gate contact Rohit Galatage, Puneet Harischandra Suvarna 2019-10-15
10446451 Method for forming replacement gate structures for vertical transistors Steven R. Soss 2019-10-15
10418368 Buried local interconnect in source/drain region Bipul C. Paul, Steven R. Soss 2019-09-17
10347745 Methods of forming bottom and top source/drain regions on a vertical transistor device Puneet Harischandra Suvarna, Daniel Chanemougame 2019-07-09
10332969 Negative capacitance matching in gate electrode structures Rohit Galatage, Puneet Harischandra Suvarna, Zoran Krivokapic 2019-06-25
10312154 Method of forming vertical FinFET device having self-aligned contacts Ruilong Xie, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann +2 more 2019-06-04