Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12419098 | Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation | Mark D. Levy, Siva P. Adusumilli | 2025-09-16 |
| 12119383 | Transistor with multi-level self-aligned gate and source/drain terminals and methods | Johnatan A. Kantarovsky, Mark D. Levy, Siva P. Adusumilli, Ajay Raman | 2024-10-15 |
| 12087764 | Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation | Mark D. Levy, Siva P. Adusumilli | 2024-09-10 |
| 12062574 | Integrated circuit structure with through-metal through-substrate interconnect and method | Zhong-Xiang He, Richard J. Rassel, Alvin J. Joseph, Ramsey Hazbun, Mark D. Levy | 2024-08-13 |
| 12002878 | Implanted isolation for device integration on a common substrate | Siva P. Adusumilli, Mark D. Levy | 2024-06-04 |
| 11916119 | Transistor with self-aligned gate and self-aligned source/drain terminal(s) and methods | Zhong-Xiang He, Ramsey Hazbun, Brett T. Cucci, Ajay Raman, Johnatan A. Kantarovsky | 2024-02-27 |
| 11881506 | Gate structures with air gap isolation features | Johnatan A. Kantarovsky, Mark D. Levy, Brett T. Cucci, Siva P. Adusumilli | 2024-01-23 |
| 11710655 | Integrated circuit structure with semiconductor-based isolation structure and methods to form same | Anthony K. Stamper, Henry L. Aldridge, Jr., Johnatan A. Kantarovsky | 2023-07-25 |
| 11646351 | Transistor with multi-level self-aligned gate and source/drain terminals and methods | Johnatan A. Kantarovsky, Mark D. Levy, Siva P. Adusumilli, Ajay Raman | 2023-05-09 |
| 11616127 | Symmetric arrangement of field plates in semiconductor devices | Johnatan A. Kantarovsky, Rajendran Krishnasamy, Siva P. Adusumilli, Steven Bentley, Michael J. Zierak | 2023-03-28 |
| 11569374 | Implanted isolation for device integration on a common substrate | Siva P. Adusumilli, Mark D. Levy | 2023-01-31 |
| 11469225 | Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation | Mark D. Levy, Siva P. Adusumilli | 2022-10-11 |
| 11316019 | Symmetric arrangement of field plates in semiconductor devices | Johnatan A. Kantarovsky, Rajendran Krishnasamy, Siva P. Adusumilli, Steven Bentley, Michael J. Zierak | 2022-04-26 |
| 11177345 | Heterojunction bipolar transistor | Henry L. Aldridge, Jr., Anthony K. Stamper, Johnatan A. Kantarovsky | 2021-11-16 |
| 11177158 | Integrated circuit structure with semiconductor-based isolation structure and methods to form same | Anthony K. Stamper, Henry L. Aldridge, Jr., Johnatan A. Kantarovsky | 2021-11-16 |
| 7993938 | Highly doped III-nitride semiconductors | William Schaff | 2011-08-09 |
| 7622322 | Method of forming an AlN coated heterojunction field effect transistor | William Schaff, Bruce M. Green | 2009-11-24 |
| 7485901 | Highly doped III-nitride semiconductors | William Schaff | 2009-02-03 |
| 7482191 | Highly doped III-nitride semiconductors | William Schaff | 2009-01-27 |
| 6953740 | Highly doped III-nitride semiconductors | William Schaff | 2005-10-11 |
| 6888170 | Highly doped III-nitride semiconductors | William Schaff | 2005-05-03 |