Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11056591 | Epitaxial structures of semiconductor devices that are independent of local pattern density | Heng Yang, Judson R. Holt | 2021-07-06 |
| 10580684 | Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same | Katherina Babich, Sunil Kumar Singh | 2020-03-03 |
| 9917103 | Diffusion break forming after source/drain forming and related IC structure | George R. Mulfinger | 2018-03-13 |
| 9899257 | Etch stop liner for contact punch through mitigation in SOI substrate | Haoren Zhuang | 2018-02-20 |
| 9887135 | Methods for providing variable feature widths in a self-aligned spacer-mask patterning process | Haoren Zhuang | 2018-02-06 |
| 9418982 | Multi-layered integrated circuit with selective temperature coefficient of resistance | Yanqing Deng, Sungjae Lee, Edward J. Nowak | 2016-08-16 |
| 9412843 | Method for embedded diamond-shaped stress element | Eric C. Harley, Judson R. Holt, Thomas A. Wallner | 2016-08-09 |
| 9171935 | FinFET formation with late fin reveal | Seong-Dong Kim, Myung-Hee Na, Thomas A. Wallner, Qintao Zhang | 2015-10-27 |
| 8940634 | Overlapping contacts for semiconductor device | Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss | 2015-01-27 |
| 8787074 | Static random access memory test structure | Oliver D. Patterson, Thomas A. Wallner, Shenzhi Yang | 2014-07-22 |
| 8124534 | Multiple exposure and single etch integration method | Thomas A. Wallner, Ying Zhang | 2012-02-28 |
| 7883953 | Method for transistor fabrication with optimized performance | Da Zhang, Voon-Yew Thean, Christopher V. Baiocco, Jie Chen, Weipeng Li +1 more | 2011-02-08 |