Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426315 | IC device with vertically-graded silicon germanium region adjacent device channel and method for forming | Judson R. Holt | 2025-09-23 |
| 12176351 | Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor | Ryan Sporer, Yusheng Bian | 2024-12-24 |
| 12154854 | Electronic fuses with a silicide layer having multiple thicknesses | Shyue Seng Tan, Eng Huat Toh | 2024-11-26 |
| 11907685 | Structure and method for random code generation | Judson R. Holt, Julien Frougier, Ryan Sporer, Daniel Jaeger | 2024-02-20 |
| 11798948 | Semiconductor structure with shared well | Kaustubh Shanbhag, Eric S. Kozarsky, Jianwei Peng | 2023-10-24 |
| 11569268 | Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor | Ryan Sporer, Yusheng Bian | 2023-01-31 |
| 11450573 | Structure with different stress-inducing isolation dielectrics for different polarity FETs | Chung Foong Tan, Ryan Sporer | 2022-09-20 |
| 11217678 | Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI | Ryan Sporer, Rick Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel | 2022-01-04 |
| 11127843 | Asymmetrical lateral heterojunction bipolar transistors | Judson R. Holt, Alexander M. Derrickson, Ryan Sporer, Alexander L. Martin, Jagar Singh | 2021-09-21 |
| 11101364 | Field-effect transistors with diffusion blocking spacer sections | Hong Yu, Man Gu, Jianwei Peng, Michael V. Aquilino | 2021-08-24 |
| 11094805 | Lateral heterojunction bipolar transistors with asymmetric junctions | Alexander M. Derrickson, Edmund K. Banghart, Alexander L. Martin, Ryan Sporer, Jagar Singh +1 more | 2021-08-17 |
| 11031484 | Silicided gate structures | Judson R. Holt, Mark V. Raymond | 2021-06-08 |
| 10825897 | Formation of enhanced faceted raised source/drain EPI material for transistor devices | Wei Hong, Hui Zang, Liu Jiang, Zhenyu Hu | 2020-11-03 |
| 10777642 | Formation of enhanced faceted raised source/drain epi material for transistor devices | Wei Hong, Hui Zang, Liu Jiang, Zhenyu Hu | 2020-09-15 |
| 10756184 | Faceted epitaxial source/drain regions | Timothy J. McArdle, Judson R. Holt, Steffen Sichler, Omur Isil Aydin, Wei Hong +3 more | 2020-08-25 |
| 10741556 | Self-aligned sacrificial epitaxial capping for trench silicide | Lakshmanan H. Vanamurthy, Scott Beasor, Timothy J. McArdle, Judson R. Holt, Hao Zhang | 2020-08-11 |
| 10680065 | Field-effect transistors with a grown silicon-germanium channel | Timothy J. McArdle, Jody A. Fronheiser, El Mehdi Bazizi, Yi Qi | 2020-06-09 |
| 10522655 | Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI | Ryan Sporer, Rick Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel | 2019-12-31 |
| 10396078 | Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same | Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park +1 more | 2019-08-27 |
| 10388654 | Methods of forming a gate-to-source/drain contact structure | Judson R. Holt, Timothy J. McArdle, Thomas Merbeth, Omur Isil Aydin, Ruilong Xie | 2019-08-20 |
| 10326007 | Post gate silicon germanium channel condensation and method for producing the same | Ryan Sporer, Timothy J. McArdle, Judson R. Holt | 2019-06-18 |
| 10236343 | Strain retention semiconductor member for channel SiGe layer of pFET | Dina H. Triyoso, Timothy J. McArdle, Judson R. Holt, Amy L. Child | 2019-03-19 |
| 10217660 | Technique for patterning active regions of transistor elements in a late manufacturing stage | Ryan Sporer | 2019-02-26 |
| 10056381 | Punchthrough stop layers for fin-type field-effect transistors | Ryan Sporer, Amy L. Child | 2018-08-21 |
| 10050119 | Method for late differential SOI thinning for improved FDSOI performance and HCI optimization | Dina H. Triyoso, Ryan Sporer | 2018-08-14 |