Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11450573 | Structure with different stress-inducing isolation dielectrics for different polarity FETs | George R. Mulfinger, Ryan Sporer | 2022-09-20 |
| 10985244 | N-well resistor | Shesh Mani Pandey, Baofu Zhu | 2021-04-20 |
| 10872979 | Spacer structures for a transistor device | Hui Zang, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie +2 more | 2020-12-22 |
| 10797049 | FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same | Hui Zang, Haiting Wang, Guowei Xu, Ruilong Xie, Scott Beasor +1 more | 2020-10-06 |
| 10629739 | Methods of forming spacers adjacent gate structures of a transistor device | Hui Zang, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie +2 more | 2020-04-21 |
| 10032902 | LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2018-07-24 |
| 9812573 | Semiconductor structure including a transistor having stress creating regions and method for the formation thereof | Arkadiusz Malinowski, Nicolas Sassiat, Maciej Wiatr | 2017-11-07 |
| 9406801 | FinFET | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2016-08-02 |
| 9219147 | LDMOS with improved breakdown voltage | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2015-12-22 |
| 9171953 | FinFET with stressors | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2015-10-27 |
| 9034711 | LDMOS with two gate stacks having different work functions for improved breakdown voltage | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2015-05-19 |
| 8975708 | Semiconductor device with reduced contact resistance and method of manufacturing thereof | Eng Huat Toh, Jae Gon Lee, Shiang Yang Ong, Elgin Quek | 2015-03-10 |
| 8969151 | Integrated circuit system employing resistance altering techniques | Shyue Seng Tan, Lee-Wee Teo, Jae Gon Lee, Elgin Quek | 2015-03-03 |
| 8896072 | Channel surface technique for fabrication of FinFET devices | Eng Huat Toh, Jae Gon Lee, Sanford Chu | 2014-11-25 |
| 8889494 | Finfet | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2014-11-18 |
| 8824208 | Non-volatile memory using pyramidal nanocrystals as electron storage elements | Elgin Quek, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee | 2014-09-02 |
| 8778772 | Method of forming transistor with increased gate width | Maciej Wiatr, Peter Javorka, Falong Zhou | 2014-07-15 |
| 8748271 | LDMOS with improved breakdown voltage | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2014-06-10 |
| 8750037 | Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof | Eng Huat Toh, Shyue Seng Tan, Jae Gon Lee, Elgin Quek | 2014-06-10 |
| 8674457 | Methods to reduce gate contact resistance for AC reff reduction | Eng Huat Toh, Elgin Quek, Chunshan Yin, Jae Gon Lee | 2014-03-18 |
| 8629503 | Asymmetrical transistor device and method of fabrication | Eng Huat Toh, Jae Gon Lee, Sanford Chu | 2014-01-14 |
| 8563386 | Integrated circuit system with bandgap material and method of manufacture thereof | Eng Huat Toh, Jae Gon Lee, Chunshan Yin, Lakshmi Kanta Bera | 2013-10-22 |
| 8530310 | Memory cell with improved retention | Lee-Wee Teo, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Elgin Quek +1 more | 2013-09-10 |
| 8502279 | Nano-electro-mechanical system (NEMS) structures with actuatable semiconductor fin on bulk substrates | Eng Huat Toh, Elgin Quek | 2013-08-06 |
| 8492235 | FinFET with stressors | Eng Huat Toh, Jae Gon Lee, Elgin Quek | 2013-07-23 |