Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10115719 | Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same | Jagar Singh | 2018-10-30 |
| 9583557 | Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime | Lili Cheng, Dina H. Triyoso, Jeasung Park, David Paul Brunco, Robert J. Fox | 2017-02-28 |
| 9530833 | Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof | Dina H. Triyoso, Johannes Mueller, Patrick Polakowski | 2016-12-27 |
| 9029227 | P-channel flash with enhanced band-to-band tunneling hot electron injection | Eng Huat Toh, Elgin Quek, Ying-Keung Leung | 2015-05-12 |
| 9006055 | High voltage FINFET structure | Han Xiao, Shaoqiang Zhang, Liming Li | 2015-04-14 |
| 8896072 | Channel surface technique for fabrication of FinFET devices | Chung Foong Tan, Eng Huat Toh, Jae Gon Lee | 2014-11-25 |
| 8664708 | EEPROM cell | Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo | 2014-03-04 |
| 8664711 | Dielectric stack | Sung Mun Jung, Swee Tuck Woo, Liang-Choo Hsia | 2014-03-04 |
| 8659067 | EEPROM cell | Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo | 2014-02-25 |
| 8629503 | Asymmetrical transistor device and method of fabrication | Chung Foong Tan, Eng Huat Toh, Jae Gon Lee | 2014-01-14 |
| 8541273 | Dielectric stack | Sung Mun Jung, Swee Tuck Woo, Liang-Choo Hsia | 2013-09-24 |
| 8410553 | Semiconductor structure including high voltage device | Jeoung Mo Koo, Purakh Raj Verma, Chunlin Zhu, Yisuo Li | 2013-04-02 |
| 8383475 | EEPROM cell | Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo | 2013-02-26 |
| 8383476 | EEPROM cell | Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo | 2013-02-26 |
| 8349692 | Channel surface technique for fabrication of FinFET devices | Chung Foong Tan, Eng Huat Toh, Jae Gon Lee | 2013-01-08 |
| 8334567 | LDMOS using a combination of enhanced dielectric stress layer and dummy gates | Yisuo Li, Guowei Zhang, Purakh Raj Verma | 2012-12-18 |
| 8324031 | Diffusion barrier and method of formation thereof | Shyue Seng Tan, Lee-Wee Teo, Yung Fu Chong, Elgin Quek | 2012-12-04 |
| 8293614 | High performance LDMOS device having enhanced dielectric strain layer | Yisuo Li, Guowei Zhang, Verma Purakh | 2012-10-23 |
| 8163621 | High performance LDMOS device having enhanced dielectric strain layer | Yisuo Li, Guowei Zhang, Verma Purakh | 2012-04-24 |
| 8110470 | Asymmetrical transistor device and method of fabrication | Chung Foong Tan, Eng Huat Toh, Jae Gon Lee | 2012-02-07 |
| 8003529 | Method of fabrication an integrated circuit | Suh Fei Lim, Kok Wai Chew, Michael Cheng | 2011-08-23 |
| 7867862 | Semiconductor structure including high voltage device | Jeoung Mo Koo, Purakh Raj Verma, Chunlin Zhu, Yisuo Li | 2011-01-11 |
| 7846805 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process | Shaoqiang Zhang, Purakh Raj Verma | 2010-12-07 |
| 7824968 | LDMOS using a combination of enhanced dielectric stress layer and dummy gates | Yisuo Li, Guowei Zhang, Purakh Raj Verma | 2010-11-02 |
| 7652355 | Integrated circuit shield structure | Suh Fei Lim, Kok Wai Chew, Michael Cheng | 2010-01-26 |