Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7488662 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process | Shaoqiang Zhang, Purakh Raj Verma | 2009-02-10 |
| 7410874 | Method of integrating triple gate oxide thickness | Purakh Raj Verma, Hwee Ngoh Chua | 2008-08-12 |
| 7382027 | MOSFET device with low gate contact resistance | Purakh Raj Verma, Lap Chan, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zhen Zheng | 2008-06-03 |
| 7323736 | Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits | Pradeep Ramachandramurthy Yelehanka, Chit Hwei Ng, Jia Zhen, Purakh Raj Verma | 2008-01-29 |
| 7250669 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks | Lap Chan, Chit Hwei Ng, Purakh Raj Verma, Jia Zhen Zheng, Johnny Kok Wai Chew +1 more | 2007-07-31 |
| 7060193 | Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits | Pradeep Ramachandramurthy Yelehanka, Chit Hwei Ng, Jia Zhen, Purakh Raj Verma | 2006-06-13 |
| 6933188 | Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies | Purakh Raj Verma, Hwee Ngoh Chua | 2005-08-23 |
| 6903013 | Method to fill a trench and tunnel by using ALD seed layer and electroless plating | Lap Chan, Chit Hwei Ng, Yong Ju, Jia Zhen Zheng | 2005-06-07 |
| 6869884 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks | Lap Chan, Chit Hwei Ng, Purakh Raj Verma, Jia Zhen Zheng, Johnny Kok Wai Chew +1 more | 2005-03-22 |
| 6861317 | Method of making direct contact on gate by using dielectric stop layer | Purakh Raj Verma, Lap Chan, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zhen Zheng | 2005-03-01 |
| 6852605 | Method of forming an inductor with continuous metal deposition | Chit Hwei Ng, Lap Chan, Purakh Raj Verma, Yelehanka Ramachandramurthy Pradeep | 2005-02-08 |
| 6835631 | Method to enhance inductor Q factor by forming air gaps below inductors | Zheng Zhen, Ng Chit Hwei, Lap Chan, Purakh Raj Verma | 2004-12-28 |
| 6825080 | Method for forming a MIM capacitor | Bin Yang, Wensheg Qian, Tan Li JIA, Chang Chuan Hu | 2004-11-30 |
| 6821904 | Method of blocking nitrogen from thick gate oxide during dual gate CMP | Yelehanka Ramachandramurthy Pradeep, Chit Hwei Ng, Jia Zhen Zheng, Purakh Raj Verma | 2004-11-23 |
| 6780727 | Method for forming a MIM (metal-insulator-metal) capacitor | Ng Chit Hwei, Shao Kai, Bao Guang Wen, Tjoa Tjin Tjin | 2004-08-24 |
| 6777774 | Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield | Sia Choon Beng, Yeo Kiat Seng, Lap Chan, Chew Kok-Wai | 2004-08-17 |
| 6746914 | Metal sandwich structure for MIM capacitor onto dual damascene | Shao Kai, Ng Chit Hwei | 2004-06-08 |
| 6730573 | MIM and metal resistor formation at CU beol using only one extra mask | Chit Hwei Ng, Chaw Sing Ho, Lup San Leong, Shao Kai, Raymond Joy +1 more | 2004-05-04 |
| 6716693 | Method of forming a surface coating layer within an opening within a body by atomic layer deposition | Lap Chan, Chit Hwei Ng, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng | 2004-04-06 |
| 6714112 | Silicon-based inductor with varying metal-to-metal conductor spacing | Sia Choon Beng, Yeo Kiat Seng | 2004-03-30 |
| 6638844 | Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill | Purakh Raj Verma, Chit Hwei, Lap Chan | 2003-10-28 |
| 6608362 | Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components | Shao Kai, Chit Hwei Ng, Jia Zhen Zheng, Sia Choon Beng, Chew Kok Wai | 2003-08-19 |
| 6576526 | Darc layer for MIM process integration | Shao Kai, Wu-Guan Ping, Chen-Wei Liang, Cheng Hua, Daniel Yen | 2003-06-10 |
| 6486017 | Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition | Purakh Raj Verma, Johnny Kok Wai Chew, Sia Choon Beng | 2002-11-26 |
| 6375857 | Method to form fuse using polymeric films | Chit Hwei Ng, Xu Yi | 2002-04-23 |