| 10336069 |
Electrically-functional optical target |
Ning Ge, Ser Chia Koh, John Patrick Oliver |
2019-07-02 |
| 10319728 |
Fluid ejection devices comprising memory cells |
Reynaldo V Villavelez, Xin Cao |
2019-06-11 |
| 9908332 |
Ink property sensing on a printhead |
Ning Ge, Adam L. Ghozeil |
2018-03-06 |
| 9559106 |
Memory cell that prevents charge loss |
Reynaldo V Villavelez, Xin Cao |
2017-01-31 |
| 9457571 |
Fluid ejection apparatuses including a substrate with a bulk layer and a epitaxial layer |
Ning Ge, Adam L. Ghozeil, Michael W. Cumbie |
2016-10-04 |
| 9252149 |
Device including active floating gate region area that is smaller than channel area |
Ning Ge, Adam L. Ghozeil, Trudy Benjamin |
2016-02-02 |
| 9199460 |
Apparatuses including a plate having a recess and a corresponding protrusion to define a chamber |
Ning Ge, Adam L. Ghozeil, Kenneth Hickey |
2015-12-01 |
| 6902981 |
Structure and process for a capacitor and other devices |
Chit Hwei Ng |
2005-06-07 |
| 6730573 |
MIM and metal resistor formation at CU beol using only one extra mask |
Chit Hwei Ng, Lup San Leong, Shao Kai, Raymond Joy, Sanford Chu +1 more |
2004-05-04 |
| 6709918 |
Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology |
Chit Hwei Ng, Jian Xun Li, Kok Wai Chew, Tjin Tjin Tjoa, Shao-fu Sanford Chu |
2004-03-23 |
| 6645810 |
Method to fabricate MIM capacitor using damascene process |
Chit Hwei Ng |
2003-11-11 |
| 6624040 |
Self-integrated vertical MIM capacitor in the dual damascene process |
Chit Hwei Ng, John E. Martin |
2003-09-23 |
| 6548367 |
Method to fabricate MIM capacitor with a curvillnear surface using damascene process |
Chit Hwei Ng |
2003-04-15 |
| 6528838 |
Damascene MIM capacitor with a curvilinear surface structure |
Chit Hwei Ng |
2003-03-04 |
| 6410376 |
Method to fabricate dual-metal CMOS transistors for sub-0.1 &mgr;m ULSI integration |
Chit Hwei Ng |
2002-06-25 |
| 6410429 |
Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions |
Kheng Chok Tee, Kin Leong Pey, G. Karunasiri, Soo Jin Chua, Kong Hean Lee +1 more |
2002-06-25 |
| 6281117 |
Method to form uniform silicide features |
Lap Chan, Fong Yau Sam Li, Hou T. Ng |
2001-08-28 |
| 6180501 |
Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process |
Kin Leong Pey, Lap Chan |
2001-01-30 |
| 6156654 |
Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices |
Yuan-Ping Lee, Chan Lap, Yong Lu, R. P.G. Karunasiri |
2000-12-05 |
| 6010954 |
Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices |
R. P.G. Karunasiri, Soo Jin Chua, Kin Leong Pey, Kong Hean Lee |
2000-01-04 |