Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847272 | Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures | Juan Boon Tan, Wei Liu, Kam Chew Leong | 2017-12-19 |
| 9837334 | Programmable active cooling device | Juan Boon Tan, Wei Liu, Kam Chew Leong | 2017-12-05 |
| 9196544 | Integrated circuits with stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating the same | Meijun Lu, Kam Chew Leong | 2015-11-24 |
| 7888752 | Structure and method to form source and drain regions over doped depletion regions | King-Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li +1 more | 2011-02-15 |
| 7528445 | Wing gate transistor for integrated circuits | Timothy Phua, Liang-Choo Hsia | 2009-05-05 |
| 7314811 | Method to make corner cross-grid structures in copper metallization | Patrick Tan, David Vigar | 2008-01-01 |
| 7238581 | Method of manufacturing a semiconductor device with a strained channel | King-Jien Chui, Ganesh Samudra, Yee-Chia Yeo, Jinping Liu, Wee Hong Phua +1 more | 2007-07-03 |
| 7202133 | Structure and method to form source and drain regions over doped depletion regions | King-Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li +1 more | 2007-04-10 |
| 7169675 | Material architecture for the fabrication of low temperature transistor | Chung Foong Tan, Jinping Liu, Hyeokjae Lee, Elgin Quek | 2007-01-30 |
| 7112866 | Method to form a cross network of air gaps within IMD layer | Lap Chan, Cher Liang Cha | 2006-09-26 |
| 7089522 | Device, design and method for a slot in a conductive area | Patrick Tan, David Vigar, Tat Wei Chua | 2006-08-08 |
| 7084025 | Selective oxide trimming to improve metal T-gate transistor | Timothy Phua, Liang-Choo Hsia | 2006-08-01 |
| 7056799 | Method of forming wing gate transistor for integrated circuits | Timothy Phua, Liang-Choo Hsia | 2006-06-06 |
| 6998682 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension | Yeen Tat Chan, Yiang Aun Nga, Zhao Lun, Wang Ling Goh, Diing Shenp Ang | 2006-02-14 |
| 6905919 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension | Yeen Tat Chan, Yiang Aun Nga, Zhao Lun, Wang Ling Goh, Diing Shenp Ang | 2005-06-14 |
| 6730571 | Method to form a cross network of air gaps within IMD layer | Lap Chan, Cher Liang Cha | 2004-05-04 |
| 6468906 | Passivation of copper interconnect surfaces with a passivating metal layer | Lap Chan, Kuan Pei Yap, Flora S. Ip, Wye Boon Loh | 2002-10-22 |
| 6410429 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions | Chaw Sing Ho, Kin Leong Pey, G. Karunasiri, Soo Jin Chua, Kong Hean Lee +1 more | 2002-06-25 |
| 6384437 | Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | Randall Cher Liang Cha, Lap Chan | 2002-05-07 |
| 6319772 | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | Randall Cher Liang Cha, Lap Chan | 2001-11-20 |
| 6268276 | Area array air gap structure for intermetal dielectric application | Lap Chan, Kok Keng Ong, Chin Hwee Seah | 2001-07-31 |
| 6251798 | Formation of air gap structures for inter-metal dielectric application | Choi Pheng Soo, Kok Keng Ong, Lap Chan | 2001-06-26 |
| 6150232 | Formation of low k dielectric | Lap Chan, Cher Liang Cha, Kok Keng Ong | 2000-11-21 |
| 6100195 | Passivation of copper interconnect surfaces with a passivating metal layer | Lap Chan, Kuan Pei Yap, Flora S. Ip, Wye Boon Loh | 2000-08-08 |