YL

Yisuo Li

CM Chartered Semiconductor Manufacturing: 8 patents #80 of 840Top 10%
GP Globalfoundries Singapore Pte.: 7 patents #107 of 828Top 15%
UP Unisantis Electronics Singapore Pte.: 7 patents #10 of 31Top 35%
Overall (All Time): #191,028 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12096608 Pillar-shaped semiconductor device and manufacturing method thereof Fujio Masuoka, Nozomu Harada 2024-09-17
11862464 Method for manufacturing three-dimensional semiconductor device Fujio Masuoka, Nozomu Harada 2024-01-02
9666688 Semiconductor device production method and semiconductor device Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Aashit Ramachandra Kamath, Zhixian Chen +3 more 2017-05-30
9490362 Semiconductor device production method and semiconductor device Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Aashit Ramachandra Kamath, Zhixian Chen +3 more 2016-11-08
9269770 Integrated circuit system with double doped drain transistor Gang Chen, Francis Benistant, Purakh Raj Verma, Hong-Seon Yang, Shao-fu Sanford Chu 2016-02-23
9153697 Surrounding gate transistor (SGT) structure Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui +7 more 2015-10-06
8609494 Surround gate CMOS semiconductor device Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang +7 more 2013-12-17
8486785 Surround gate CMOS semiconductor device Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang +7 more 2013-07-16
8410553 Semiconductor structure including high voltage device Jeoung Mo Koo, Purakh Raj Verma, Sanford Chu, Chunlin Zhu 2013-04-02
8334567 LDMOS using a combination of enhanced dielectric stress layer and dummy gates Sanford Chu, Guowei Zhang, Purakh Raj Verma 2012-12-18
8293614 High performance LDMOS device having enhanced dielectric strain layer Sanford Chu, Guowei Zhang, Verma Purakh 2012-10-23
8163621 High performance LDMOS device having enhanced dielectric strain layer Sanford Chu, Guowei Zhang, Verma Purakh 2012-04-24
7951680 Integrated circuit system employing an elevated drain Guowei Zhang, Ming-Shuan Li, Purakh Raj Verma, Shao-fu Sanford Chu 2011-05-31
7888752 Structure and method to form source and drain regions over doped depletion regions King-Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Kum Woh Vincent Leong +1 more 2011-02-15
7867862 Semiconductor structure including high voltage device Jeoung Mo Koo, Purakh Raj Verma, Sanford Chu, Chunlin Zhu 2011-01-11
7824968 LDMOS using a combination of enhanced dielectric stress layer and dummy gates Sanford Chu, Guowei Zhang, Purakh Raj Verma 2010-11-02
7573099 Semiconductor device layout and channeling implant process Xiaohong Jiang, Francis Benistant 2009-08-11
7259072 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability Francis Benistant, Kim Sik, Zhao Lun 2007-08-21
7253483 Semiconductor device layout and channeling implant process Xiaohong Jiang, Francis Benistant 2007-08-07
7202133 Structure and method to form source and drain regions over doped depletion regions King-Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Kum Woh Vincent Leong +1 more 2007-04-10
7101743 Low cost source drain elevation through poly amorphizing implant technology Francis Benistant, Kian Meng Tee, King-Jien Chui 2006-09-05
6972236 Semiconductor device layout and channeling implant process Xiaohong Jiang, Francis Benistant 2005-12-06