Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164099 | Device with diffusion blocking layer in source/drain region | Shesh Mani Pandey, Pei Zhao, Baofu Zhu | 2018-12-25 |
| 9997225 | System and method for modular simulation of spin transfer torque magnetic random access memory devices | Deepanjan Datta, Bhagawan Sahu | 2018-06-12 |
| 9966433 | Multiple-step epitaxial growth S/D regions for NMOS FinFET | Zhiqing Li, Shesh Mani Pandey | 2018-05-08 |
| 9947788 | Device with diffusion blocking layer in source/drain region | Shesh Mani Pandey, Pei Zhao, Baofu Zhu | 2018-04-17 |
| 9871132 | Extended drain metal-oxide-semiconductor transistor | Kun Liu, Xiaoping Wang, Li Cao | 2018-01-16 |
| 9673084 | Isolation scheme for high voltage device | Kun Liu, Ming-Shuan Li, Namchil Mun, Shiang Yang Ong, Purakh Raj Verma | 2017-06-06 |
| 9577040 | FinFET conformal junction and high epi surface dopant concentration method and device | Peijie Feng, Jianwei Peng, Yanxiang Liu, Shesh Mani Pandey | 2017-02-21 |
| 9559176 | FinFET conformal junction and abrupt junction with reduced damage method and device | Peijie Feng, Yanxiang Liu, Shesh Mani Pandey, Jianwei Peng | 2017-01-31 |
| 9406752 | FinFET conformal junction and high EPI surface dopant concentration method and device | Peijie Feng, Jianwei Peng, Yanxiang Liu, Shesh Mani Pandey | 2016-08-02 |
| 9397162 | FinFET conformal junction and abrupt junction with reduced damage method and device | Peijie Feng, Yanxiang Liu, Shesh Mani Pandey, Jianwei Peng | 2016-07-19 |
| 9269770 | Integrated circuit system with double doped drain transistor | Yisuo Li, Gang Chen, Purakh Raj Verma, Hong-Seon Yang, Shao-fu Sanford Chu | 2016-02-23 |
| 8994107 | Semiconductor devices and methods of forming the semiconductor devices including a retrograde well | El Mehdi Bazizi | 2015-03-31 |
| 8860142 | Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction | Debora Chyiu Hyia Poon, Alex See, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou +1 more | 2014-10-14 |
| 8354321 | Method for fabricating semiconductor devices with reduced junction diffusion | Benjamin Colombeau, Sai-Hooi Yeong, Bangun Indajang, Lap Chan | 2013-01-15 |
| 8293544 | Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction | Debora Chyiu Hyia Poon, Alex See, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou +1 more | 2012-10-23 |
| 8053340 | Method for fabricating semiconductor devices with reduced junction diffusion | Benjamin Colombeau, Sai-Hooi Yeong, Bangun Indajang, Lap Chan | 2011-11-08 |
| 7888752 | Structure and method to form source and drain regions over doped depletion regions | King-Jien Chui, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong +1 more | 2011-02-15 |
| 7573099 | Semiconductor device layout and channeling implant process | Yisuo Li, Xiaohong Jiang | 2009-08-11 |
| 7271435 | Modified source/drain re-oxidation method and system | Paul Rudeck, Kelly Hurley | 2007-09-18 |
| 7259072 | Shallow low energy ion implantation into pad oxide for improving threshold voltage stability | Yisuo Li, Kim Sik, Zhao Lun | 2007-08-21 |
| 7253483 | Semiconductor device layout and channeling implant process | Yisuo Li, Xiaohong Jiang | 2007-08-07 |
| 7202133 | Structure and method to form source and drain regions over doped depletion regions | King-Jien Chui, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong +1 more | 2007-04-10 |
| 7101743 | Low cost source drain elevation through poly amorphizing implant technology | Yisuo Li, Kian Meng Tee, King-Jien Chui | 2006-09-05 |
| 7037860 | Modified source/drain re-oxidation method and system | Paul Rudeck, Kelly Hurley | 2006-05-02 |
| 6972236 | Semiconductor device layout and channeling implant process | Yisuo Li, Xiaohong Jiang | 2005-12-06 |