Issued Patents All Time
Showing 25 most recent of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11802370 | Method for decolorizing textiles | Edwin Yee Man Keh, Lei Yao, Hok Chung Chan, Sai Lung Fung, Un Teng Lam +1 more | 2023-10-31 |
| 8354321 | Method for fabricating semiconductor devices with reduced junction diffusion | Benjamin Colombeau, Sai-Hooi Yeong, Francis Benistant, Bangun Indajang | 2013-01-15 |
| 8053340 | Method for fabricating semiconductor devices with reduced junction diffusion | Benjamin Colombeau, Sai-Hooi Yeong, Francis Benistant, Bangun Indajang | 2011-11-08 |
| 7935632 | Reduced metal pipe formation in metal silicide contacts | Wei Tong, K. Suresh Kumar, Miow Chin Tan | 2011-05-03 |
| 7932152 | Method of forming a gate stack structure | Will K. Wong, Alan Lek | 2011-04-26 |
| 7888224 | Method for forming a shallow junction region using defect engineering and laser annealing | Kuang Kian Ong, Sai-Hooi Yeong, Kin Leong Pey, Yung Fu Chong | 2011-02-15 |
| 7573081 | Method to fabricate horizontal air columns underneath metal inductor | Kok Wai Chew, Cher Liang Cha, Chee Tee Chua | 2009-08-11 |
| 7570144 | Integrated transformer and method of fabrication thereof | Chee Chong Lim, Kok Wai Chew, Kiat Seng Yeo, Suh Fei Lim, Manh Anh Do | 2009-08-04 |
| 7382027 | MOSFET device with low gate contact resistance | Purakh Raj Verma, Sanford Chu, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zhen Zheng | 2008-06-03 |
| 7313780 | System and method for designing semiconductor photomasks | Andrew Khoh, Byong-Il Choi, Ganesh Samudra, Yihong Wu | 2007-12-25 |
| 7250669 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks | Sanford Chu, Chit Hwei Ng, Purakh Raj Verma, Jia Zhen Zheng, Johnny Kok Wai Chew +1 more | 2007-07-31 |
| 7238971 | Self-aligned lateral heterojunction bipolar transistor | Jian Xun Li, Purakh Raj Verma, Jia Zhen Zheng, Shao-fu Sanford Chu | 2007-07-03 |
| 7112866 | Method to form a cross network of air gaps within IMD layer | Cher Liang Cha, Kheng Chok Tee | 2006-09-26 |
| 7105420 | Method to fabricate horizontal air columns underneath metal inductor | Kok Wai Chew, Cher Liang Cha, Chee Tee Chua | 2006-09-12 |
| 7060573 | Extended poly buffer STI scheme | Victor Lim, Feng Chen, Wang Ling Goh | 2006-06-13 |
| 7049201 | Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy | Purakh Raj Verma, Shao-fu Sanford Chu, Jian Xun Li, Jia Zhen Zheng | 2006-05-23 |
| 7037791 | Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates | Lay Cheng Choo, James Yong Meng Lee | 2006-05-02 |
| 7030451 | Method and apparatus for performing nickel salicidation | Pooi See Lee, Kin Leong Pey, Alex See | 2006-04-18 |
| 7022578 | Heterojunction bipolar transistor using reverse emitter window | Purakh Raj Verma, Shao-fu Sanford Chu, Jian Xun Li, Zhen Jia Zheng | 2006-04-04 |
| 6972237 | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth | Purakh Raj Verma, Shao-fu Sanford Chu, Jia Zhen Zheng, Jian Xun Li | 2005-12-06 |
| 6962850 | Process to manufacture nonvolatile MOS memory device | Vincent Ho, Wee Kiong Choi, Wai Kin Chim, Vivian Ng, Cheng Lin Heng +1 more | 2005-11-08 |
| 6924202 | Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact | Jian Xun Li, Purakh Raj Verma, Jia Zhen Zheng, Shao-fu Sanford Chu | 2005-08-02 |
| 6908824 | Self-aligned lateral heterojunction bipolar transistor | Jian Xun Li, Purakh Raj Verma, Jia Zhen Zheng, Shao-fu Sanford Chu | 2005-06-21 |
| 6903013 | Method to fill a trench and tunnel by using ALD seed layer and electroless plating | Sanford Chu, Chit Hwei Ng, Yong Ju, Jia Zhen Zheng | 2005-06-07 |
| 6899857 | Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique | Soo Choi Pheng, Wang Cui Yang, Siew Yong Kong, Alex See | 2005-05-31 |