Issued Patents All Time
Showing 51–75 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495200 | Method to deposit a seeding layer for electroless copper plating | Fong Yau Sam Li, Hou T. Ng | 2002-12-17 |
| 6483148 | Self-aligned elevated transistor | Cher Liang Cha | 2002-11-19 |
| 6468906 | Passivation of copper interconnect surfaces with a passivating metal layer | Kuan Pei Yap, Kheng Chok Tee, Flora S. Ip, Wye Boon Loh | 2002-10-22 |
| 6468877 | Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-10-22 |
| 6461900 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-10-08 |
| 6461887 | Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-10-08 |
| 6455377 | Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) | Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-09-24 |
| 6440800 | Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek +2 more | 2002-08-27 |
| 6436774 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek +2 more | 2002-08-20 |
| 6436770 | Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation | Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan +2 more | 2002-08-20 |
| 6432797 | Simplified method to reduce or eliminate STI oxide divots | Randall Cher Liang Cha, Tae Jong Lee, Alex See, Yeow Kheng Lim | 2002-08-13 |
| 6417056 | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-07-09 |
| 6417054 | Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide | Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-07-09 |
| 6406945 | Method for forming a transistor gate dielectric with high-K and low-K regions | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek +2 more | 2002-06-18 |
| 6403485 | Method to form a low parasitic capacitance pseudo-SOI CMOS device | Elgin Quek, Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying Keung +2 more | 2002-06-11 |
| 6403484 | Method to achieve STI planarization | Victor Lim, James Yong Meng Lee, Chen Feng, Wang Ling Goh | 2002-06-11 |
| 6387747 | Method to fabricate RF inductors with minimum area | Randall Cher Liang Cha, Tae Jong Lee, Alex See, Chua Chee Tee | 2002-05-14 |
| 6387784 | Method to reduce polysilicon depletion in MOS transistors | Yung Fu Chong, Randall Cher Liang Cha, Kin Leong Pey | 2002-05-14 |
| 6384437 | Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | Kheng Chok Tee, Randall Cher Liang Cha | 2002-05-07 |
| 6380088 | Method to form a recessed source drain on a trench side wall with a replacement gate technique | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-04-30 |
| 6355563 | Versatile copper-wiring layout design with low-k dielectric integration | Randall Cher Liang Cha, Alex See, Yeow Kheng Lim, Tae Jong Lee | 2002-03-12 |
| 6348385 | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant | Randall Cher Liang Cha, Tae Jong Lee, Alex See, Chee Tee Chua | 2002-02-19 |
| 6326272 | Method for forming self-aligned elevated transistor | Cher Liang Cha | 2001-12-04 |
| 6323125 | Simplified dual damascene process utilizing PPMSO as an insulator layer | Choi Pheng Soo, Wye Boon Loh | 2001-11-27 |
| 6319772 | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | Kheng Chok Tee, Randall Cher Liang Cha | 2001-11-20 |