Issued Patents All Time
Showing 101–125 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6204137 | Method to form transistors and local interconnects using a silicon nitride dummy gate technique | Kok Hin Teo, Feng Chen, Alex See | 2001-03-20 |
| 6180501 | Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process | Kin Leong Pey, Chaw Sing Ho | 2001-01-30 |
| 6177324 | ESD protection device for STI deep submicron technology | Jun Song, Shyue Fong Quek, Ting Cheong Ang | 2001-01-23 |
| 6165869 | Method to avoid dishing in forming trenches for shallow trench isolation | Gang Qian, Chock Hing Gan, Poh Suan Tan | 2000-12-26 |
| 6150232 | Formation of low k dielectric | Cher Liang Cha, Kok Keng Ong, Kheng Chok Tee | 2000-11-21 |
| 6143598 | Method of fabrication of low leakage capacitor | John E. Martin, John Sudijono, Ting Cheong Ang | 2000-11-07 |
| 6140237 | Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer | Jia Zhen Zheng | 2000-10-31 |
| 6136693 | Method for planarized interconnect vias using electroless plating and CMP | Hou T. Ng | 2000-10-24 |
| 6121135 | Modified buried contact process for IC device fabrication | Yong Kong Siew | 2000-09-19 |
| 6121130 | Laser curing of spin-on dielectric thin films | Chee Tee Chua, Yuan-Ping Lee, Mei Sheng Zhou | 2000-09-19 |
| 6110787 | Method for fabricating a MOS device | Ting Cheong Ang, Shyue Pong Quek, Sang Yee Loong | 2000-08-29 |
| 6103594 | Method to form shallow trench isolations | Alex See | 2000-08-15 |
| 6103569 | Method for planarizing local interconnects | Kok Hin Teo, Feng Chen | 2000-08-15 |
| 6100196 | Method of making a copper interconnect with top barrier layer | Jia Zhen Zheng | 2000-08-08 |
| 6100195 | Passivation of copper interconnect surfaces with a passivating metal layer | Kuan Pei Yap, Kheng Chok Tee, Flora S. Ip, Wye Boon Loh | 2000-08-08 |
| 6093628 | Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application | Chong Wee Lim, Kin Leong Pey, Soh Yun Siah, Eng Hwa Lim | 2000-07-25 |
| 6069069 | Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop | Simon Chooi, Jia Zhen Zheng | 2000-05-30 |
| 6064201 | Method and apparatus to image metallic patches embedded in a non-metal surface | Cher Liang Cha, Hao Gong, Eng Fong Chor | 2000-05-16 |
| 6051467 | Method to fabricate a large planar area ONO interpoly dielectric in flash device | Cher Liang Cha | 2000-04-18 |
| 6001706 | Method for making improved shallow trench isolation for semiconductor integrated circuits | Poh Suan Tan, Qinghua Zhong, Qian Gang | 1999-12-14 |
| 5948700 | Method of planarization of an intermetal dielectric layer using chemical mechanical polishing | Jia Zhen Zheng | 1999-09-07 |
| 5923075 | Definition of anti-fuse cell for programmable gate array application | Che-Chia Wei, Bob Lee, Pom Suan Tan | 1999-07-13 |
| 5893787 | Application of fast etching glass for FED manufacturing | Simon Chooi | 1999-04-13 |
| 5870121 | Ti/titanium nitride and ti/tungsten nitride thin film resistors for thermal ink jet technology | — | 1999-02-09 |
| 5858870 | Methods for gap fill and planarization of intermetal dielectrics | Jai Zhen Zheng, Simon Chooi | 1999-01-12 |