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CM Chartered Semiconductor Manufacturing: 122 patents #2 of 840Top 1%
NS National University Of Singapore: 23 patents #4 of 1,623Top 1%
NS Nanyang Technological University Of Singapore: 4 patents #1 of 17Top 6%
IM Institute Of Microelectronics: 3 patents #18 of 153Top 15%
NU Nanyang Technological University: 2 patents #168 of 1,285Top 15%
GP Globalfoundries Singapore Pte.: 2 patents #291 of 828Top 40%
TL The Hong Kong Research Institute Of Textiles And Apparel Limited: 1 patents #24 of 108Top 25%
📍 Singapore, CA: #7 of 327 inventorsTop 3%
Overall (All Time): #8,829 of 4,157,543Top 1%
127
Patents All Time

Issued Patents All Time

Showing 76–100 of 127 patents

Patent #TitleCo-InventorsDate
6319767 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique Randall Cher Liang Cha, Tae Jong Lee, Alex See, Yeow Kheng Lim 2001-11-20
6313008 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan +2 more 2001-11-06
6306714 Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide Yang Pan, James Yongmeng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more 2001-10-23
6306715 Method to form smaller channel with CMOS device by isotropic etching of the gate materials Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more 2001-10-23
6303418 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer Cher Liang Cha, Alex See 2001-10-16
6303449 Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more 2001-10-16
6300177 Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more 2001-10-09
6300172 Method of field isolation in silicon-on-insulator technology Ting Cheong Ang, Shyue Pong Quek, Sang Yee Loong 2001-10-09
6297109 Method to form shallow junction transistors while eliminating shorts due to junction spiking Cher Liang Cha, Ravishankar Sundaresan 2001-10-02
6284610 Method to reduce compressive stress in the silicon substrate during silicidation Randall Cher Liang Cha, Chee Tee Chua, Kin Leong Pey 2001-09-04
6281117 Method to form uniform silicide features Chaw Sing Ho, Fong Yau Sam Li, Hou T. Ng 2001-08-28
6274485 Method to reduce dishing in metal chemical-mechanical polishing Feng Chen, Rick Teo 2001-08-14
6275089 Low voltage controllable transient trigger network for ESD protection Jun Song, Ting Cheong Ang, Shyue Fong Quek 2001-08-14
6268276 Area array air gap structure for intermetal dielectric application Kheng Chok Tee, Kok Keng Ong, Chin Hwee Seah 2001-07-31
6261935 Method of forming contact to polysilicon gate for MOS devices Alex See, Ravi Sundaresan 2001-07-17
6251798 Formation of air gap structures for inter-metal dielectric application Choi Pheng Soo, Kheng Chok Tee, Kok Keng Ong 2001-06-26
6251781 Method to deposit a platinum seed layer for use in selective copper plating Mei Sheng Zhou, Guo Qin Xu 2001-06-26
6252277 Embedded polysilicon gate MOSFET Cher Liang Cha, Eng Fong Chor, Gong Hao, Teck Koon Lee 2001-06-26
6252290 Method to form, and structure of, a dual damascene interconnect device Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong 2001-06-26
6248659 Method for forming an interconnect structure Randall Liang 2001-06-19
6225225 Method to form shallow trench isolation structures for borderless contacts in an integrated circuit Kenny Hua Kooi Goh, Kok Siong Yap 2001-05-01
6221560 Method to enhance global planarization of silicon oxide surface for IC device fabrication Choi Pheng Soo 2001-04-24
6221727 Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology Johnny Kok Wai Chew, Cher Liang Cha, Chee Tee Chua 2001-04-24
6214728 Method to encapsulate copper plug for interconnect metallization Sam Fong Yau Li, Hou T. Ng 2001-04-10
6207534 Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing Cher Liang Cha, Teck Koon Lee 2001-03-27