Issued Patents All Time
Showing 26–50 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6890854 | Method and apparatus for performing nickel salicidation | Pooi See Lee, Kin Leong Pey, Alex See | 2005-05-10 |
| 6881976 | Heterojunction BiCMOS semiconductor | Jia Zhen Zheng, Shao-fu Sanford Chu | 2005-04-19 |
| 6878623 | Technique to achieve thick silicide film for ultra-shallow junctions | Cheng Tan, Randall Cher Liang Cha, Alex See | 2005-04-12 |
| 6869884 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks | Sanford Chu, Chit Hwei Ng, Purakh Raj Verma, Jia Zhen Zheng, Johnny Kok Wai Chew +1 more | 2005-03-22 |
| 6869857 | Method to achieve STI planarization | Feng-Wei Dai, Pang Choong Hau, Peter Hing | 2005-03-22 |
| 6861317 | Method of making direct contact on gate by using dielectric stop layer | Purakh Raj Verma, Sanford Chu, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zhen Zheng | 2005-03-01 |
| 6852605 | Method of forming an inductor with continuous metal deposition | Chit Hwei Ng, Purakh Raj Verma, Yelehanka Ramachandramurthy Pradeep, Sanford Chu | 2005-02-08 |
| 6835631 | Method to enhance inductor Q factor by forming air gaps below inductors | Zheng Zhen, Sanford Chu, Ng Chit Hwei, Purakh Raj Verma | 2004-12-28 |
| 6777329 | Method to form C54 TiSi2 for IC device fabrication | Shaoyin Chen, Ze Shen, Alex See | 2004-08-17 |
| 6747314 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy +2 more | 2004-06-08 |
| 6730571 | Method to form a cross network of air gaps within IMD layer | Cher Liang Cha, Kheng Chok Tee | 2004-05-04 |
| 6716693 | Method of forming a surface coating layer within an opening within a body by atomic layer deposition | Sanford Chu, Chit Hwei Ng, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng | 2004-04-06 |
| 6709934 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek +2 more | 2004-03-23 |
| 6696761 | Method to encapsulate copper plug for interconnect metallization | Sam Fong Yau Li, Hou T. Ng | 2004-02-24 |
| 6680239 | Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant | Cher Liang Cha, Kok Keng Ong, Alex See | 2004-01-20 |
| 6638844 | Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill | Purakh Raj Verma, Sanford Chu, Chit Hwei | 2003-10-28 |
| 6566650 | Incorporation of dielectric layer onto SThM tips for direct thermal analysis | Chang Chaun Hu, Kin Leong Pey, Yung Fu Chong, Chim Wai Kin, Pavel Neuzil | 2003-05-20 |
| 6566215 | Method of fabricating short channel MOS transistors with source/drain extensions | Yung Fu Chong | 2003-05-20 |
| 6566209 | Method to form shallow junction transistors while eliminating shorts due to junction spiking | Cher Liang Cha, Ravishankar Sundaresan | 2003-05-20 |
| 6566208 | Method to form elevated source/drain using poly spacer | Yang Pan, Lee Yong Meng, Leung Keung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more | 2003-05-20 |
| 6544824 | Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2003-04-08 |
| 6541327 | Method to form self-aligned source/drain CMOS device on insulated staircase oxide | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2003-04-01 |
| 6531750 | Shallow junction transistors which eliminating shorts due to junction spiking | Cher Liang Cha, Ravishankar Sundaresan | 2003-03-11 |
| 6511884 | Method to form and/or isolate vertical transistors | Elgin Quek, Ravi Sundaresan, Yang Pan, Yong Meng Lee, Ying-Keung Leung +2 more | 2003-01-28 |
| 6501122 | Flash device having a large planar area ono interpoly dielectric | Cher Liang Cha | 2002-12-31 |