Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE41670 | Sram cell fabrication with interlevel Dielectric planarization | Loi N. Nguyen | 2010-09-14 |
| 6812142 | Method and interlevel dielectric structure for improved metal step coverage | Loi N. Nguyen | 2004-11-02 |
| 6753576 | Method of fabricating a one-sided polysilicon thin film transistor | — | 2004-06-22 |
| 6566209 | Method to form shallow junction transistors while eliminating shorts due to junction spiking | Lap Chan, Cher Liang Cha | 2003-05-20 |
| 6531750 | Shallow junction transistors which eliminating shorts due to junction spiking | Lap Chan, Cher Liang Cha | 2003-03-11 |
| 6297109 | Method to form shallow junction transistors while eliminating shorts due to junction spiking | Lap Chan, Cher Liang Cha | 2001-10-02 |
| 6190179 | Method of making a field effect transistor having a channel in an epitaxial silicon layer | — | 2001-02-20 |
| 6107642 | SRAM cell with thin film transistor using two polysilicon layers | — | 2000-08-22 |
| 5990528 | Thin film transistor with titanium nitride or refractory metal gate in SRAM device serving as source/drain contact electrode of an independent FET | — | 1999-11-23 |
| 5861643 | Self-aligned JFET | Tony Chen | 1999-01-19 |
| 5723988 | CMOS with parasitic bipolar transistor | Shivaling S. Mahant-Shetti, Mark G. Harward, Lawrence A. Arledge, Jr. | 1998-03-03 |
| 5721163 | Method of manufacture of thin film transistor SRAM device with a titanium nitride or silicide gate | — | 1998-02-24 |
| 5710461 | SRAM cell fabrication with interlevel dielectric planarization | Loi N. Nguyen | 1998-01-20 |
| 5702987 | Method of manufacture of self-aligned JFET | Wei Tony Chen | 1997-12-30 |
| 5686334 | Method of making SRAM cell with thin film transistor using two polysilicon layers | — | 1997-11-11 |
| 5554548 | Method of fabricating a one-sided polysilicon thin film transistor | — | 1996-09-10 |
| 5395785 | SRAM cell fabrication with interlevel dielectric planarization | Loi N. Nguyen | 1995-03-07 |
| 5346839 | Sidewall doping technique for SOI transistors | — | 1994-09-13 |
| 5347152 | Stacked CMOS latch with cross-coupled capacitors | — | 1994-09-13 |
| 5304504 | Method of forming a gate overlap LDD structure | Che-Chia Wei | 1994-04-19 |
| 5298782 | Stacked CMOS SRAM cell with polysilicon transistor load | — | 1994-03-29 |
| 5294823 | SOI BICMOS process | Robert H. Eklund | 1994-03-15 |
| 5293053 | Elevated CMOS | Satwinder S. Malhi, Shivaling S. Mahant-Shetti | 1994-03-08 |
| 5292670 | Sidewall doping technique for SOI transistors | — | 1994-03-08 |
| 5276347 | Gate overlapping LDD structure | Che-Chia Wei | 1994-01-04 |