Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12425112 | Signal power validator | Rand C. Chandler, Aiden J. Cowhig, Robert N. Iannuzzi, Joseph A. Moder, Michael O'Brien +2 more | 2025-09-23 |
| 11837509 | Method of manufacturing and packaging silicon photonics integrated circuit dies in wafer form | Hsu-Feng Chou, Keith Nellis | 2023-12-05 |
| RE45286 | Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming | Olivier Le Neel, Peyman Sana, Venkatesh Mohanakrishnaswamy | 2014-12-09 |
| 8853850 | MEMS packaging scheme using dielectric fence | Venkatesh Mohanakrishnaswamy, Venkata Ramana Yogi Mallela | 2014-10-07 |
| 8853802 | Method of forming a die having an IC region adjacent a MEMS region | Venkatesh Mohanakrishnaswamy, Olivier Le Neel | 2014-10-07 |
| 8680631 | High aspect ratio capacitively coupled MEMS devices | Venkatesh Mohanakrishnaswamy | 2014-03-25 |
| 8432006 | High aspect ratio capacitively coupled MEMS devices | Venkatesh Mohanakrishnaswamy | 2013-04-30 |
| 8405202 | MEMS packaging scheme using dielectric fence | Venkatesh Mohanakrishnaswamy, Venkata Ramana Yogi Mallela | 2013-03-26 |
| 8193595 | Method of forming a die having an IC region adjacent a MEMS region | Venkatesh Mohanakrishnaswamy, Olivier Le Neel | 2012-06-05 |
| 8022491 | High aspect ratio all SiGe capacitively coupled MEMS devices | Venkatesh Mohanakrishnaswamy | 2011-09-20 |
| 7943410 | Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming | Olivier Le Neel, Peyman Sana, Venkatesh Mohanakrishnaswamy | 2011-05-17 |
| RE41670 | Sram cell fabrication with interlevel Dielectric planarization | Ravishankar Sundaresan | 2010-09-14 |
| 6812142 | Method and interlevel dielectric structure for improved metal step coverage | Ravishankar Sundaresan | 2004-11-02 |
| 6661064 | Memory masking for periphery salicidation of active regions | Robert Louis Hodges | 2003-12-09 |
| 6518620 | EEPROM memory cell with increased dielectric integrity | Tsiu C. Chan, Pervez Hassan Sagarwala | 2003-02-11 |
| 6514811 | Method for memory masking for periphery salicidation of active regions | Robert Louis Hodges | 2003-02-04 |
| 6472261 | Method of forming an integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure | — | 2002-10-29 |
| 6284584 | Method of masking for periphery salicidation of active regions | Robert Louis Hodges | 2001-09-04 |
| 6251713 | Method of making an SRAM storage cell with N channel thin film transistor load devices | Tsiu C. Chan | 2001-06-26 |
| RE36938 | Method of forming a landing pad structure in an integrated circuit | Tsiu C. Chan, Frank R. Bryant | 2000-10-31 |
| 6107194 | Method of fabricating an integrated circuit | Robert Louis Hodges | 2000-08-22 |
| 6096634 | Method of patterning a submicron semiconductor layer | — | 2000-08-01 |
| 6093963 | Dual landing pad structure including dielectric pocket | Tsiu C. Chan, Frank R. Bryant, Artur P. Balasinski | 2000-07-25 |
| 6057604 | Integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure | — | 2000-05-02 |
| 6051864 | Memory masking for periphery salicidation of active regions | Robert Louis Hodges | 2000-04-18 |