Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE41068 | Spacer-type thin-film polysilicon transistor for low-power memory devices | Kuei-Wu Huang | 2010-01-05 |
| 7231374 | Scheme for evaluating costs and/or benefits of manufacturing technologies | — | 2007-06-12 |
| 6681376 | Integrated scheme for semiconductor device verification | Linard Karklin, Valery Axelrad | 2004-01-20 |
| 6562638 | Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout | Robert C. Pack, Valery Axelrad, Victor Boksha | 2003-05-13 |
| 6093963 | Dual landing pad structure including dielectric pocket | Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen | 2000-07-25 |
| 5960311 | Method for forming controlled voids in interlevel dielectric | Abha Singh, Ming Li | 1999-09-28 |
| 5945738 | Dual landing pad structure in an integrated circuit | Loi N. Nguyen, Frank R. Bryant | 1999-08-31 |
| 5909636 | Method of forming a landing pad structure in an integrated circuit | Loi N. Nguyen, Frank R. Bryant | 1999-06-01 |
| 5847464 | Method for forming controlled voids in interlevel dielectric | Abha Singh, Ming Li | 1998-12-08 |
| 5804472 | Method of making spacer-type thin-film polysilicon transistor for low-power memory devices | Kuei-Wu Huang | 1998-09-08 |
| 5795800 | Integrated circuit fabrication method with buried oxide isolation | Tsiu C. Chan | 1998-08-18 |
| 5705427 | Method of forming a landing pad structure in an integrated circuit | Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen | 1998-01-06 |
| 5640023 | Spacer-type thin-film polysilicon transistor for low-power memory devices | Kuei-Wu Huang | 1997-06-17 |