| 10431422 |
Method and system for dimensional uniformity using charged particle beam lithography |
Akira Fujimura, Kazuyuki Hagiwara |
2019-10-01 |
| 10055535 |
Method, system and program product for identifying anomalies in integrated circuit design layouts |
Piyush Pathak, Wei-Long Wang, Karthik Krishnamoorthy, Fadi Batarseh, Uwe Schroeder +1 more |
2018-08-21 |
| 9859100 |
Method and system for dimensional uniformity using charged particle beam lithography |
Akira Fujimura, Kazuyuki Hagiwara |
2018-01-02 |
| 9343267 |
Method and system for dimensional uniformity using charged particle beam lithography |
Akira Fujimura, Kazuyuki Hagiwara |
2016-05-17 |
| 9038003 |
Method and system for critical dimension uniformity using charged particle beam lithography |
Ryan Pearman, Akira Fujimura |
2015-05-19 |
| 8959463 |
Method and system for dimensional uniformity using charged particle beam lithography |
Akira Fujimura, Kazuyuki Hagiwara, Anatoly Aadamov |
2015-02-17 |
| 8745549 |
Method and system for forming high precision patterns using charged particle beam lithography |
Akira Fujimura |
2014-06-03 |
| 8468482 |
Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits |
William Wai Yan Ho |
2013-06-18 |
| 8453102 |
Hierarchical variation analysis of integrated circuits |
William Wai Yan Ho |
2013-05-28 |
| 8407627 |
Method and system for context-specific mask inspection |
Louis K. Scheffer |
2013-03-26 |
| 7784016 |
Method and system for context-specific mask writing |
Louis K. Scheffer |
2010-08-24 |
| 7302672 |
Method and system for context-specific mask writing |
Louis K. Scheffer |
2007-11-27 |
| 7249342 |
Method and system for context-specific mask writing |
Louis K. Scheffer |
2007-07-24 |
| 7231628 |
Method and system for context-specific mask inspection |
Louis K. Scheffer |
2007-06-12 |
| 7024638 |
Method for creating patterns for producing integrated circuits |
Louis K. Scheffer, Kenji Yoshida, Yoshikuni Abe, Aki Fujimura |
2006-04-04 |
| 6562638 |
Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout |
Artur P. Balasinski, Valery Axelrad, Victor Boksha |
2003-05-13 |
