VB

Victor Boksha

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Cypress Semiconductor: 1 patents #1,072 of 1,852Top 60%
📍 Los Altos, CA: #2,722 of 3,651 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
Overall (All Time): #3,511,146 of 4,157,543Top 85%
1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6562638 Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout Artur P. Balasinski, Robert C. Pack, Valery Axelrad 2003-05-13