Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10381360 | Control gate dummy for word line uniformity and method for producing the same | Laiqiang Luo, Sen Mei, Fangxin Deng, Zhiqiang Teo, Fan Zhang +3 more | 2019-08-13 |
| 9318378 | Slot designs in wide metal lines | Yeow Kheng Lim, Alex See, Tae Jong Lee, David Vigar, Liang-Choo Hsia | 2016-04-19 |
| 9024286 | RRAM cell with bottom electrode(s) positioned in a semiconductor substrate | Wenhu Liu, Nagarajan Raghavan, Chee Mang Ng | 2015-05-05 |
| 8922003 | Low OHMIC contacts | Dexter Xueming Tan, Yoke King Chin | 2014-12-30 |
| 8338280 | Method for fabricating nano devices | Dexter Xueming Tan, Sai-Hooi Yeong, Yoke King Chin, Kuang Kian Ong, Chee Mang Ng | 2012-12-25 |
| 8101487 | Method for fabricating semiconductor devices with shallow diffusion regions | Dexter Xueming Tan, Benjamin Colombeau, Clark Kuang Kian Ong, Sai-Hooi Yeong, Chee Mang Ng | 2012-01-24 |
| 7892905 | Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing | Kuang Kian Ong, King-Jien Chui, Ganesh Samudra, Yee-Chia Yeo, Yung Fu Chong | 2011-02-22 |
| 7888224 | Method for forming a shallow junction region using defect engineering and laser annealing | Kuang Kian Ong, Sai-Hooi Yeong, Lap Chan, Yung Fu Chong | 2011-02-15 |
| 7253097 | Integrated circuit system using dual damascene process | Yeow Kheng Lim, Chim Seng Seet, Tae Jong Lee, Liang-Choo Hsia | 2007-08-07 |
| 7030451 | Method and apparatus for performing nickel salicidation | Pooi See Lee, Alex See, Lap Chan | 2006-04-18 |
| 7005716 | Dual metal gate process: metals and their silicides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2006-02-28 |
| 6890854 | Method and apparatus for performing nickel salicidation | Pooi See Lee, Alex See, Lap Chan | 2005-05-10 |
| 6891233 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2005-05-10 |
| 6835989 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2004-12-28 |
| 6750519 | Dual metal gate process: metals and their silicides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2004-06-15 |
| 6677652 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2004-01-13 |
| 6624489 | Formation of silicided shallow junctions using implant through metal technology and laser annealing process | Yung Fu Chong, Alex See | 2003-09-23 |
| 6566650 | Incorporation of dielectric layer onto SThM tips for direct thermal analysis | Chang Chaun Hu, Yung Fu Chong, Chim Wai Kin, Pavel Neuzil, Lap Chan | 2003-05-20 |
| 6534388 | Method to reduce variation in LDD series resistance | Wenhe Lin, Zhong Dong, Simon Chooi | 2003-03-18 |
| 6534390 | Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure | Yung Fu Chong, Randall Cher Liang Cha | 2003-03-18 |
| 6524910 | Method of forming dual thickness gate dielectric structures via use of silicon nitride layers | Wenhe Lin, Mei Sheng Zhou, Zhong Dong, Simon Chooi | 2003-02-25 |
| 6475908 | Dual metal gate process: metals and their silicides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2002-11-05 |
| 6458695 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Mei Sheng Zhou, Simon Chooi | 2002-10-01 |
| 6410429 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions | Chaw Sing Ho, Kheng Chok Tee, G. Karunasiri, Soo Jin Chua, Kong Hean Lee +1 more | 2002-06-25 |
| 6391731 | Activating source and drain junctions and extensions using a single laser anneal | Yung Fu Chong, Alex See | 2002-05-21 |