Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414343 | Semiconductor device with different sized epitaxial structures | Hong Yu | 2025-09-09 |
| 12389616 | Transistors with multiple silicide layers | Man Gu, Hong Yu, Haiting Wang | 2025-08-12 |
| 12020937 | Carbon implantation for thicker gate silicide | Hong Yu, Man Gu, Eric S. Kozarsky | 2024-06-25 |
| 11935928 | Bipolar transistor with self-aligned asymmetric spacer | Hong Yu, Vibhor Jain | 2024-03-19 |
| 11810951 | Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials | Hong Yu, Viorel Ontalus | 2023-11-07 |
| 11798948 | Semiconductor structure with shared well | Kaustubh Shanbhag, Eric S. Kozarsky, George R. Mulfinger | 2023-10-24 |
| 11554993 | Highly thixotropic 3D printing concrete and manufacturing method therefor | Jun Wu, Hai HUANG, Juan Chen, Qiang Yuan, Jie Tang +4 more | 2023-01-17 |
| 11111054 | Equal-fork pallet | Qiaoli Wu, Huizhen Jiang | 2021-09-07 |
| 11101364 | Field-effect transistors with diffusion blocking spacer sections | George R. Mulfinger, Hong Yu, Man Gu, Michael V. Aquilino | 2021-08-24 |
| 10910471 | Device with large EPI in FinFETs and method of manufacturing | Sang Woo Lim, Matthew W. Stoker, Huang Liu, Jinping Liu | 2021-02-02 |
| 10836071 | Method for processing a molded tray based on bamboo shavings | Huizhen Jiang | 2020-11-17 |
| 10784342 | Single diffusion breaks formed with liner protection for source and drain regions | Wei Hong, Hong Yu, Hui Zhan | 2020-09-22 |
| 10773417 | Method for processing a molded tray based on bamboo-wood mixed shavings | Huizhen Jiang | 2020-09-15 |
| D887665 | Supporting plate | — | 2020-06-16 |
| 10468310 | Spacer integration scheme for FNET and PFET devices | Xusheng Wu | 2019-11-05 |
| 10453754 | Diffused contact extension dopants in a transistor device | Haigou Huang, Qun Gao, Xin Wang | 2019-10-22 |
| 10446483 | Metal-insulator-metal capacitors with enlarged contact areas | Sipeng Gu, Xusheng Wu, Yi Qi, Jeffrey Chee | 2019-10-15 |
| 10431665 | Multiple-layer spacers for field-effect transistors | Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo | 2019-10-01 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie | 2019-09-10 |
| 10297675 | Dual-curvature cavity for epitaxial semiconductor growth | Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianghu Yan, Yi Qi | 2019-05-21 |
| 10276689 | Method of forming a vertical field effect transistor (VFET) and a VFET structure | Yi Qi, Hsien-Ching Lo, Ruilong Xie, Xunyuan Zhang, Hui Zang | 2019-04-30 |
| 10262903 | Boundary spacer structure and integration | Judson R. Holt, Yi Qi, Hsien-Ching Lo | 2019-04-16 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Hsien-Ching Lo, Wei Hong, Yanping Shen, Yongjun Shi +5 more | 2019-04-02 |
| 10224330 | Self-aligned junction structures | Xusheng Wu | 2019-03-05 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Xusheng Wu, Sipeng Gu, Hsien-Ching Lo | 2019-02-19 |