Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957799 | Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions | Ruilong Xie, Julien Frougier, Chanro Park, Edward J. Nowak, Kangguo Cheng +1 more | 2021-03-23 |
| 10903369 | Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions | Ruilong Xie, Julien Frougier, Chanro Park, Edward J. Nowak, Kangguo Cheng +1 more | 2021-01-26 |
| 10756184 | Faceted epitaxial source/drain regions | George R. Mulfinger, Timothy J. McArdle, Judson R. Holt, Steffen Sichler, Omur Isil Aydin +3 more | 2020-08-25 |
| 10700173 | FinFET device with a wrap-around silicide source/drain contact structure | Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong, Xing Zhang +4 more | 2020-06-30 |
| 10680065 | Field-effect transistors with a grown silicon-germanium channel | George R. Mulfinger, Timothy J. McArdle, Jody A. Fronheiser, El Mehdi Bazizi | 2020-06-09 |
| 10643845 | Repaired mask structures and resultant underlying patterned structures | Xunyuan Zhang, Ruilong Xie | 2020-05-05 |
| 10636894 | Fin-type transistors with spacers on the gates | Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti +4 more | 2020-04-28 |
| 10559656 | Wrap-all-around contact for nanosheet-FET and method of forming same | Emilie Bourjot, Julien Frougier, Ruilong Xie, Hui Zang, Hsien-Ching Lo +1 more | 2020-02-11 |
| 10546775 | Field-effect transistors with improved dielectric gap fill | Wei Hong, Liu Jiang, Yongjun Shi, Hsien-Ching Lo, Hui Zang | 2020-01-28 |
| 10483172 | Transistor device structures with retrograde wells in CMOS applications | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Puneet Khanna, Srikanth B. Samavedam +2 more | 2019-11-19 |
| 10461155 | Epitaxial region for embedded source/drain region having uniform thickness | Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong +6 more | 2019-10-29 |
| 10446483 | Metal-insulator-metal capacitors with enlarged contact areas | Sipeng Gu, Jianwei Peng, Xusheng Wu, Jeffrey Chee | 2019-10-15 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Jianwei Peng, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie | 2019-09-10 |
| 10381459 | Transistors with H-shaped or U-shaped channels and method for forming the same | Ruilong Xie, Julien Frougier, Nigel G. Cave, Edward J. Nowak, Andreas Knorr | 2019-08-13 |
| 10355104 | Single-curvature cavity for semiconductor epitaxy | Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu +3 more | 2019-07-16 |
| 10297675 | Dual-curvature cavity for epitaxial semiconductor growth | Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan | 2019-05-21 |
| 10276689 | Method of forming a vertical field effect transistor (VFET) and a VFET structure | Jianwei Peng, Hsien-Ching Lo, Ruilong Xie, Xunyuan Zhang, Hui Zang | 2019-04-30 |
| 10262903 | Boundary spacer structure and integration | Judson R. Holt, Hsien-Ching Lo, Jianwei Peng | 2019-04-16 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Hsien-Ching Lo, Jianwei Peng, Wei Hong, Yanping Shen, Yongjun Shi +5 more | 2019-04-02 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven R. Soss +8 more | 2019-02-26 |
| 10211147 | Metal-insulator-metal capacitors with dielectric inner spacers | Xunyuan Zhang, Chanro Park, Lei Sun, Roderick A. Augur | 2019-02-19 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Xusheng Wu, Jianwei Peng, Sipeng Gu, Hsien-Ching Lo | 2019-02-19 |
| 10170473 | Forming long channel FinFET with short channel vertical FinFET and related integrated circuit | Hui Zang, Josef S. Watts | 2019-01-01 |
| 10163635 | Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method | Hui Zang, Hsien-Ching Lo, Jerome Ciavatti, Judson R. Holt | 2018-12-25 |
| 10164010 | Finfet diffusion break having protective liner in fin insulator | Wei Hong, Hsien-Ching Lo, Haiting Wang, Yanping Shen, Yongjun Shi +2 more | 2018-12-25 |