Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10644149 | LDMOS fin-type field-effect transistors including a dummy gate | Jagar Singh | 2020-05-05 |
| 10636894 | Fin-type transistors with spacers on the gates | Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Yi Qi +4 more | 2020-04-28 |
| 10593754 | SOI device structures with doped regions providing charge sinking | Jagar Singh, Jae Gon Lee, Josef S. Watts | 2020-03-17 |
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu +3 more | 2019-11-12 |
| 10418365 | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array | Hui Zang, Rinus Tek Po Lee | 2019-09-17 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Ruilong Xie | 2019-09-10 |
| 10373877 | Methods of forming source/drain contact structures on integrated circuit products | Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong +3 more | 2019-08-06 |
| 10290712 | LDMOS finFET structures with shallow trench isolation inside the fin | Jagar Singh, Hui Zang | 2019-05-14 |
| 10211206 | Two-port vertical SRAM circuit structure and method for producing the same | Hui Zang | 2019-02-19 |
| 10164006 | LDMOS FinFET structures with trench isolation in the drain extension | Jagar Singh, Hui Zang | 2018-12-25 |
| 10163635 | Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method | Yi Qi, Hui Zang, Hsien-Ching Lo, Judson R. Holt | 2018-12-25 |
| 10163915 | Vertical SRAM structure | Hui Zang | 2018-12-25 |
| 10134739 | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array | Hui Zang, Rinus Tek Po Lee | 2018-11-20 |
| 10121878 | LDMOS finFET structures with multiple gate structures | Jagar Singh, Hui Zang | 2018-11-06 |
| 10121893 | Integrated circuit structure without gate contact and method of forming same | Hui Zang, Manfred Eller, Min-hwa Chi | 2018-11-06 |
| 10068902 | Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method | Yanping Shen, Hui Zang, Hsien-Ching Lo, Yongjun Shi, Randy W. Mann +4 more | 2018-09-04 |
| 10026740 | DRAM structure with a single diffusion break | Hui Zang, Josef S. Watts | 2018-07-17 |
| 9876010 | Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure | Hui Zang, Jagar Singh | 2018-01-23 |
| 9842927 | Integrated circuit structure without gate contact and method of forming same | Hui Zang, Manfred Eller, Min-hwa Chi | 2017-12-12 |
| 9773781 | Resistor and capacitor disposed directly upon a SAC cap of a gate structure of a semiconductor structure | Hui Zang, Jagar Singh | 2017-09-26 |
| 9666709 | Non-planar semiconductor structure with preserved isolation region | Xiaoli He, Yanxiang Liu, Myung-Hee Nam | 2017-05-30 |
| 9601578 | Non-planar vertical dual source drift metal-oxide semiconductor (VDSMOS) | Yanxiang Liu, Vara Govindeswara Reddy Vakada | 2017-03-21 |
| 9543298 | Single diffusion break structure and cuts later method of making | Hui Zang, Min-hwa Chi | 2017-01-10 |
| 9536991 | Single diffusion break structure | Hui Zang, Min-hwa Chi | 2017-01-03 |
| 9397191 | Methods of making a self-aligned channel drift device | Yanxiang Liu | 2016-07-19 |