Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957578 | Single diffusion break device for FDSOI | Wei Hong, Hui Zang, Zhenyu Hu, Liu Jiang | 2021-03-23 |
| 10714577 | Etch stop layer for use in forming contacts that extend to multiple depths | Wei Hong, Hui Zang | 2020-07-14 |
| 10700173 | FinFET device with a wrap-around silicide source/drain contact structure | Yi Qi, Hong Yu, Yanping Shen, Wei Hong, Xing Zhang +4 more | 2020-06-30 |
| 10636894 | Fin-type transistors with spacers on the gates | Yanping Shen, Hui Zang, Qun Gao, Jerome Ciavatti, Yi Qi +4 more | 2020-04-28 |
| 10559656 | Wrap-all-around contact for nanosheet-FET and method of forming same | Emilie Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang +1 more | 2020-02-11 |
| 10553707 | FinFETs having gates parallel to fins | Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee +1 more | 2020-02-04 |
| 10546775 | Field-effect transistors with improved dielectric gap fill | Wei Hong, Liu Jiang, Yongjun Shi, Yi Qi, Hui Zang | 2020-01-28 |
| 10461155 | Epitaxial region for embedded source/drain region having uniform thickness | Yoong Hooi Yong, Yanping Shen, Xusheng Wu, Joo Tat Ong, Wei Hong +6 more | 2019-10-29 |
| 10431665 | Multiple-layer spacers for field-effect transistors | Tao Han, Zhenyu Hu, Jinping Liu, Jianwei Peng | 2019-10-01 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Jianwei Peng, Yi Qi, Jerome Ciavatti, Ruilong Xie | 2019-09-10 |
| 10388652 | Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same | Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann +4 more | 2019-08-20 |
| 10355104 | Single-curvature cavity for semiconductor epitaxy | Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao +3 more | 2019-07-16 |
| 10297675 | Dual-curvature cavity for epitaxial semiconductor growth | Alina Vinslava, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi | 2019-05-21 |
| 10276689 | Method of forming a vertical field effect transistor (VFET) and a VFET structure | Yi Qi, Jianwei Peng, Ruilong Xie, Xunyuan Zhang, Hui Zang | 2019-04-30 |
| 10262903 | Boundary spacer structure and integration | Judson R. Holt, Yi Qi, Jianwei Peng | 2019-04-16 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Jianwei Peng, Wei Hong, Yanping Shen, Yongjun Shi +5 more | 2019-04-02 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Xusheng Wu, Jianwei Peng, Sipeng Gu | 2019-02-19 |
| 10164010 | Finfet diffusion break having protective liner in fin insulator | Wei Hong, Haiting Wang, Yanping Shen, Yi Qi, Yongjun Shi +2 more | 2018-12-25 |
| 10163635 | Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method | Yi Qi, Hui Zang, Jerome Ciavatti, Judson R. Holt | 2018-12-25 |
| 10121868 | Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device | Yi Qi, Jianwei Peng, Kwan-Yong Lim, Hui Zhan | 2018-11-06 |
| 10068810 | Multiple Fin heights with dielectric isolation | Xusheng Wu, Yi Qi, Jianwei Peng, Sipeng Gu | 2018-09-04 |
| 10068902 | Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method | Yanping Shen, Hui Zang, Yongjun Shi, Randy W. Mann, Yi Qi +4 more | 2018-09-04 |
| 10050125 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Hui Zang, Xusheng Wu | 2018-08-14 |
| 9947769 | Multiple-layer spacers for field-effect transistors | Tao Han, Zhenyu Hu, Jinping Liu, Jianwei Peng | 2018-04-17 |
| 9887094 | Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device | Yi Qi, Jianwei Peng, Yanping Shen, Hui Zhan | 2018-02-06 |