Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12389627 | Silicon germanium fins and integration methods | Hong Yu, Haiting Wang | 2025-08-12 |
| 12364000 | Device structures for a high-voltage semiconductor device | Hong Yu, David Pritchard, Navneet Jain | 2025-07-15 |
| 12272740 | Bipolar junction transistors with a nanosheet intrinsic base | Haiting Wang, Hong Yu | 2025-04-08 |
| 12261215 | Fin on silicon-on-insulator | Hong Yu, Haiting Wang | 2025-03-25 |
| 12205949 | High-voltage semiconductor device structures | Hong Yu, Haiting Wang | 2025-01-21 |
| 12159926 | Lateral bipolar transistor | Haiting Wang, Alexander M. Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr +2 more | 2024-12-03 |
| 12107154 | Single fin structures | Haiting Wang, Hong Yu | 2024-10-01 |
| 11908898 | Lateral bipolar transistor structure with base layer of varying horizontal width and methods to form same | Haiting Wang, Hong Yu, Alexander M. Derrickson | 2024-02-20 |
| 11888031 | Fin-based lateral bipolar junction transistor and method | Hong Yu, Judson R. Holt | 2024-01-30 |
| D1006095 | Projector | Haitian Wang, Gang Zhao, Sidney Wilson Nai, Enyang Zhu, Jiachen Liu | 2023-11-28 |
| 11810969 | Lateral bipolar transistor | Haiting Wang, Alexander M. Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr +2 more | 2023-11-07 |
| 11784224 | Lateral bipolar transistor structure with base over semiconductor buffer and related method | Hong Yu, Jagar Singh, John J. Pekarik | 2023-10-10 |
| 11705508 | Single fin structures | Haiting Wang, Hong Yu | 2023-07-18 |
| D987705 | Projector | Luwei Ma, Dilong He, Qianshang Chen, Yusen Wang, Haitian Wang +3 more | 2023-05-30 |
| 11264470 | Lateral bipolar junction transistor device and method of making such a device | Haiting Wang, Tamilmani Ethirajan, Tung-Hsing Lee | 2022-03-01 |
| 11127842 | Single fin structures | Haiting Wang, Hong Yu | 2021-09-21 |
| 10957578 | Single diffusion break device for FDSOI | Wei Hong, Hui Zang, Hsien-Ching Lo, Liu Jiang | 2021-03-23 |
| 10833067 | Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure | Haiting Wang, Sipeng Gu, Jiehui Shu, Scott Beasor | 2020-11-10 |
| 10825897 | Formation of enhanced faceted raised source/drain EPI material for transistor devices | Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang | 2020-11-03 |
| 10777642 | Formation of enhanced faceted raised source/drain epi material for transistor devices | Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang | 2020-09-15 |
| 10707303 | Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts | Haiting Wang, Hui Zang | 2020-07-07 |
| 10692039 | Cargo logistics dispatch service with integrated pricing and scheduling | Pawan R. Chowdhary, Markus Ettl, Roger D. Lederman, Zhengliang Xue | 2020-06-23 |
| 10643900 | Method to reduce FinFET short channel gate height | Xinyuan Dou, Hong Yu, Xing Zhang | 2020-05-05 |
| 10559656 | Wrap-all-around contact for nanosheet-FET and method of forming same | Emilie Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang +1 more | 2020-02-11 |
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Scott Beasor +3 more | 2019-11-12 |