Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879180 | FinFET with etch-selective spacer and self-aligned contact capping layer | Hui Zang, Guowei Xu, Ruilong Xie | 2020-12-29 |
| 10872979 | Spacer structures for a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong +2 more | 2020-12-22 |
| 10833067 | Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure | Haiting Wang, Sipeng Gu, Jiehui Shu, Zhenyu Hu | 2020-11-10 |
| 10832839 | Metal resistors with a non-planar configuration | Haiting Wang, Sipeng Gu, Jiehui Shu | 2020-11-10 |
| 10832965 | Fin reveal forming STI regions having convex shape between fins | Yiheng Xu, Haiting Wang, Qun Gao, Kyung-Bum Koo, Ankur Arya | 2020-11-10 |
| 10832966 | Methods and structures for a gate cut | Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Yang | 2020-11-10 |
| 10818659 | FinFET having upper spacers adjacent gate and source/drain contacts | Haiting Wang, Hui Zang, Guowei Xu | 2020-10-27 |
| 10818557 | Integrated circuit structure to reduce soft-fail incidence and method of forming same | Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil Kumar Singh, Ravi Prakash Srivastava +1 more | 2020-10-27 |
| 10804379 | FinFET device and method of manufacturing | Hui Zang, Ruilong Xie | 2020-10-13 |
| 10797049 | FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same | Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie +1 more | 2020-10-06 |
| 10763176 | Transistor with a gate structure comprising a tapered upper surface | Hui Zang, Haiting Wang | 2020-09-01 |
| 10741556 | Self-aligned sacrificial epitaxial capping for trench silicide | George R. Mulfinger, Lakshmanan H. Vanamurthy, Timothy J. McArdle, Judson R. Holt, Hao Zhang | 2020-08-11 |
| 10707175 | Asymmetric overlay mark for overlay measurement | Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang +1 more | 2020-07-07 |
| 10636890 | Chamfered replacement gate structures | Haiting Wang, Rongtao Lu, Chih-Chiang Chang, Guowei Xu, Hui Zang +1 more | 2020-04-28 |
| 10629694 | Gate contact and cross-coupling contact formation | Hui Zang, Ruilong Xie, Haiting Wang | 2020-04-21 |
| 10629739 | Methods of forming spacers adjacent gate structures of a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong +2 more | 2020-04-21 |
| 10600914 | Isolation pillar first gate structures and methods of forming same | Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren +2 more | 2020-03-24 |
| 10586736 | Hybrid fin cut with improved fin profiles | Haiting Wang, Ruilong Xie, Shesh Mani Pandey, Hui Zang, Garo Derderian | 2020-03-10 |
| 10580701 | Methods of making a self-aligned gate contact structure and source/drain metallization structures on integrated circuit products | Hui Zang, Haiting Wang | 2020-03-03 |
| 10522644 | Different upper and lower spacers for contact | Guowei Xu, Hui Zang, Haiting Wang | 2019-12-31 |
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu +3 more | 2019-11-12 |
| 10403742 | Field-effect transistors with fins formed by a damascene-like process | Wei Zhao, Haiting Wang, David Paul Brunco, Jiehui Shu, Shesh Mani Pandey +1 more | 2019-09-03 |
| 10373877 | Methods of forming source/drain contact structures on integrated circuit products | Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong +3 more | 2019-08-06 |
| 10361289 | Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same | Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu +4 more | 2019-07-23 |
| 10326002 | Self-aligned gate contact and cross-coupling contact formation | Hui Zang, Ruilong Xie, Zhenyu Hu | 2019-06-18 |