Issued Patents All Time
Showing 1–25 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879171 | Vertically oriented metal silicide containing e-fuse device | Chun Yu Wong, Seong Yeol Mun, Jagar Singh, Hui Zang | 2020-12-29 |
| 10580779 | Vertical transistor static random access memory cell | Ryan Ryoung-Han Kim | 2020-03-03 |
| 10529724 | Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures | Hui Zang, Manfred Eller | 2020-01-07 |
| 10510662 | Vertically oriented metal silicide containing e-fuse device and methods of making same | Chun Yu Wong, Seong Yeol Mun, Jagar Singh, Hui Zang | 2019-12-17 |
| 10468481 | Self-aligned single diffusion break isolation with reduction of strain loss | Haiting Wang, Hui Zang, Chun Yu Wong | 2019-11-05 |
| 10297672 | Triple gate technology for 14 nanometer and onwards | Seong Yeol Mun, Kijik Lee | 2019-05-21 |
| 10290738 | Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device | Ruilong Xie, Christopher M. Prindle | 2019-05-14 |
| 10243073 | Vertical channel field-effect transistor (FET) process compatible long channel transistors | Brent A. Anderson, Steven Bentley, Hiroaki Niimi, Junli Wang | 2019-03-26 |
| 10236291 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie | 2019-03-19 |
| 10163900 | Integration of vertical field-effect transistors and saddle fin-type field effect transistors | Ruilong Xie, Min Gyu Sung | 2018-12-25 |
| 10141446 | Formation of bottom junction in vertical FET devices | Hiroaki Niimi, Steven Bentley, Daniel Chanemougame | 2018-11-27 |
| 10121868 | Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device | Yi Qi, Jianwei Peng, Hsien-Ching Lo, Hui Zhan | 2018-11-06 |
| 10083971 | Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts | Hui Zang, Manfred Eller | 2018-09-25 |
| 10068978 | Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression | Christopher M. Prindle | 2018-09-04 |
| 10008499 | Method to form silicide and contact at embedded epitaxial facet | James Walter Blatchford, Shashank S. Ekbote, Younsung Choi | 2018-06-26 |
| 9960086 | Methods, apparatus and system for self-aligned retrograde well doping for finFET devices | Mira Park, Steven Bentley, Amitabh Jain | 2018-05-01 |
| 9929236 | Active area shapes reducing device size | Bipul C. Paul | 2018-03-27 |
| 9911738 | Vertical-transport field-effect transistors with a damascene gate strap | Hiroaki Niimi, Brent A. Anderson, Junli Wang | 2018-03-06 |
| 9865704 | Single and double diffusion breaks on integrated circuit products comprised of FinFET devices | Ruilong Xie, Min Gyu Sung, Ryan Ryoung-Han Kim | 2018-01-09 |
| 9859125 | Block patterning method enabling merged space in SRAM with heterogeneous mandrel | Min Gyu Sung, Ruilong Xie, Chanro Park, Hoon Kim | 2018-01-02 |
| 9847418 | Methods of forming fin cut regions by oxidizing fin portions | Min Gyu Sung, Chanro Park | 2017-12-19 |
| 9842933 | Formation of bottom junction in vertical FET devices | Hiroaki Niimi, Steven Bentley, Daniel Chanemougame | 2017-12-12 |
| 9837404 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie | 2017-12-05 |
| 9812452 | Method to form silicide and contact at embedded epitaxial facet | James Walter Blatchford, Shashank S. Ekbote, Younsung Choi | 2017-11-07 |
| 9799751 | Methods of forming a gate structure on a vertical transistor device | John H. Zhang, Steven Bentley | 2017-10-24 |