Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11251093 | Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow | Steven Lee Prins | 2022-02-15 |
| 10734290 | Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow | Steven Lee Prins | 2020-08-04 |
| 10559469 | Dual pocket approach in PFETs with embedded SI-GE source/drain | — | 2020-02-11 |
| 10134643 | Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow | Steven Lee Prins | 2018-11-20 |
| 10026837 | Embedded SiGe process for multi-threshold PMOS transistors | Deborah J. Riley | 2018-07-17 |
| 10008499 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote | 2018-06-26 |
| 9947765 | Dummy gate placement methodology to enhance integrated circuit performance | Shashank S. Ekbote, Gregory Charles Baldwin | 2018-04-17 |
| 9812452 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote | 2017-11-07 |
| 9735159 | Optimized layout for relaxed and strained liner in single stress liner technology | Greg Baldwin | 2017-08-15 |
| 9583488 | Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow | Steven Lee Prins | 2017-02-28 |
| 9508601 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote | 2016-11-29 |
| 9496142 | Dummy gate placement methodology to enhance integrated circuit performance | Shashank S. Ekbote, Gregory Charles Baldwin | 2016-11-15 |
| 8438526 | Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions | Gregory Charles Baldwin, Oluwamuyiwa Oluwagbemiga Olubuyide | 2013-05-07 |