Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11974421 | SRAM layout for double patterning | — | 2024-04-30 |
| 10840250 | SRAM layout for double patterning | — | 2020-11-17 |
| 10741489 | Rectangular via for ensuring via yield in the absence of via redundancy | — | 2020-08-11 |
| 10181474 | SRAM layout for double patterning | — | 2019-01-15 |
| 10103153 | SRAM layout for double patterning | — | 2018-10-16 |
| 10103171 | Metal on elongated contacts | Scott Jessen | 2018-10-16 |
| 10043714 | Elongated contacts using litho-freeze-litho-etch process | Scott Jessen | 2018-08-07 |
| 10008499 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, Shashank S. Ekbote, Younsung Choi | 2018-06-26 |
| 9899364 | Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two | Thomas J. Aton | 2018-02-20 |
| 9812452 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, Shashank S. Ekbote, Younsung Choi | 2017-11-07 |
| 9620419 | Elongated contacts using litho-freeze-litho-etch process | Scott Jessen | 2017-04-11 |
| 9508601 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, Shashank S. Ekbote, Younsung Choi | 2016-11-29 |
| 9312170 | Metal on elongated contacts | Scott Jessen | 2016-04-12 |
| 9305848 | Elongated contacts using litho-freeze-litho-etch process | Scott Jessen | 2016-04-05 |
| 9178038 | Raised source/drain MOS transistor and method of forming the transistor with an implant spacer and an epitaxial spacer | Seung-Chul Song, Kwan-Yong Lim | 2015-11-03 |
| 9123562 | Layout method to minimize context effects and die area | Thomas J. Aton | 2015-09-01 |
| 9112000 | Method for ensuring DPT compliance for auto-routed via layers | — | 2015-08-18 |
| 9024450 | Two-track cross-connect in double-patterned structure using rectangular via | Scott Jessen | 2015-05-05 |
| 8828833 | System for controlling SiGe-to-gate spacing | Chet V. Lenox | 2014-09-09 |
| 8756550 | Method to ensure double patterning technology compliance in standard cells | — | 2014-06-17 |
| 8751977 | Method for generating ultra-short-run-length dummy poly features | — | 2014-06-10 |
| 8745548 | Perturbational technique for co-optimizing design rules and illumination conditions for lithography process | — | 2014-06-03 |
| 8707223 | Method for ensuring DPT compliance with autorouted metal layers | — | 2014-04-22 |
| 8703608 | Control of local environment for polysilicon conductors in integrated circuits | Yong-Seok Choi | 2014-04-22 |
| 8667432 | Gate CD control using local design on both sides of neighboring dummy gate level features | Yong-Seok Choi, Thomas J. Aton | 2014-03-04 |